R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 186

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 157 of 573
14. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system.
14.1
Table 14.1
Note:
Count source
Count operation
Count start condition
Count stop condition
Watchdog timer
initialization conditions
Operations at underflow
Selectable functions
The watchdog timer contains a 14-bit counter and allows selection of count source protection mode enable or
disable.
Table 14.1 lists the Watchdog Timer Specifications.
Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.
Figure 14.1 shows a Watchdog Timer Block Diagram.
1. Write the WDTR register during the count operation of the watchdog timer.
Overview
Item
Watchdog Timer Specifications
Decrement
• Division ratio of the prescaler
CPU clock
Either of the following can be selected:
• After a reset, count starts automatically
• Count starts by writing to the WDTS register
Stop mode, wait mode
• Reset
• Write 00h and then FFh to the WDTR register (with acknowledgement period
• Underflow
Watchdog timer interrupt
or watchdog timer reset
• Count source protection mode
• Start or stop of the watchdog timer after a reset
• Initial value of the watchdog timer
• Refresh acknowledgement period for the watchdog timer
setting)
Selected by the WDTC7 bit in the WDTC register or the CM07 bit in
the CM0 register.
Whether count source protection mode is enabled or disabled after a reset
can be selected by the CSPROINI bit in the OFS register (flash memory).
If count source protection mode is disabled after a reset, it can be enabled or
disabled by the CSPRO bit in the CSPR register (program).
Selected by the WDTON bit in the OFS register (flash memory).
Selectable by bits WDTUFS0 and WDTUFS1 in the OFS2 register.
Selectable by bits WDTRCS0 and WDTRCS1 in the OFS2 register.
Count Source Protection Mode
(1)
Disabled
Low-speed on-chip oscillator clock
for the watchdog timer
None
Watchdog timer reset
Count Source Protection Mode
Enabled
14. Watchdog Timer