R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 278

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 249 of 573
19.5
Table 19.9
j = A, B, C, or D
Count source
Count operation
Count period
Waveform output timing
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC, and
TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D)
match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The output
compare function, or other mode or function, can be selected for each individual pin.
Table 19.9 lists the Specifications of Output Compare Function, Figure 19.9 shows a Block Diagram of Output
Compare Function, Table 19.10 lists the Functions of TRCGRj Register when Using Output Compare Function,
and Figure 19.10 shows an Operating Example of Output Compare Function.
Timer Mode (Output Compare Function)
Item
Specifications of Output Compare Function
Compare match
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
External signal (rising edge) input to TRCCLK pin
Increment
• The CCLR bit in the TRCCR1 register is set to 0 (free running operation):
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to 0000h at
1 (count starts) is written to the TSTART bit in the TRCMR register.
• When the CSEL bit in the TRCCR2 register is set to 0 (count continues after
• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
Programmable I/O port or output compare output (Selectable individually for
each pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt
input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• Output compare output pin selection
• Compare match output level selection
• Initial output level selection
• Timing for setting the TRC register to 0000h
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse
• Can be used as an internal timer by disabling timer RC output
• Changing output pins for registers TRCGRC and TRCGRD
• A/D trigger generation
1/fk × 65,536
fk: Count source frequency
TRCGRA compare match):
1/fk × (n + 1)
n: TRCGRA register setting value
compare match with TRCGRA).
0 (count stops) is written to the TSTART bit in the TRCMR register.
The output compare output pin retains output level before count stops, the TRC
register retains a value before count stops.
match with TRCGRA register).
The count stops at the compare match with the TRCGRA register. The output
compare output pin retains the level after the output is changed by the compare
match.
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
“L” output, “H” output, or toggle output
Sets output level for period from count start to compare match
Overflow or compare match with the TRCGRA register
Output.)
TRCGRC can be used for output control of the TRCIOA pin and TRCGRD can
be used for output control of the TRCIOB pin.
Specification
19. Timer RC