R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 286

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 257 of 573
Figure 19.12
TRCSR register
TRCSR register
TRCSR register
TRCSR register
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer register).
• Bits EA and EB in the TRCOER register are set to 0 (enable TRCIOA and TRCIOB pin outputs).
• The CCLR bit in the TRCCR1 register are set to 1 (set the TRC register to 0000h by compare match in the TRCGRA register).
• Bits TOA and TOB in the TRCCR1 register are set to 0 (initial output “L” to compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA register compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 011b (TRCIOB output inverted at TRCGRB register compare match).
• Bits IOC2 to IOC0 in the TRCIOR1 register are set to 011b (TRCIOA output inverted at TRCGRC register compare match).
• The IOC3 bit in the TRCIOR1 register are set to 0 (TRCIOA output register).
• Bits IOD2 to IOD0 in the TRCIOR1 register are set to 011b (TRCIOB output inverted at TRCGRD register compare match).
• The IOD3 bit in the TRCIOR1 register are set to 0 (TRCIOB output register).
• The CSEL bit in the TRCCR2 register are set to 0 (TRC continues counting after compare match).
TRCIOA output
TRCIOB output
IMFC bit in
IMFD bit in
Count source
IMFA bit in
IMFB bit in
Value in TRC register
Operating Example When TRCGRC Register is Used for Output Control of TRCIOA
Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin
FFFFh
0000h
Initial output “L”
Initial output “L”
m
n
p
q
Output inverted by compare match
Set to 0 by a program
Output inverted by compare match
Set to 0 by a program
q+1
p+1
n+1
p-q
m+1
Set to 0 by a program
m: Value set in TRCGRA register
n: Value set in TRCGRC register
p: Value set in TRCGRB register
q: Value set in TRCGRD register
Set to 0 by a program
m-n
19. Timer RC

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