R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 301

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 272 of 573
19.8
Figure 19.20
Table 19.15
Timer RC Status Register
Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC
register (bits IR and ILVL0 to ILVL2) and a single vector.
Table 19.15 lists the Registers Associated with Timer RC Interrupt, and Figure 19.20 is a Timer RC Interrupt Block
Diagram.
Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because
a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.
• The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to 1
• The IR bit is set to 0 (no interrupt requested) when the bit in the TRCSR register or the corresponding bit in
• If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not
• If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the
• The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to
Refer to 19.2.4 Timer RC Interrupt Enable Register (TRCIER), for details of the TRCIER register.
Refer to 11.3 Interrupt Control, for details of the TRCIC register and 11.1.5.2 Relocatable Vector Tables,
for information on interrupt vectors.
and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained if
the IR bit is once set to 1 but the interrupt is not acknowledged.
change.
interrupt request.
0 within the interrupt routine. Refer to 19.2.5 Timer RC Status Register (TRCSR), for the procedure for
setting these bits to 0.
Timer RC Interrupt
TRCSR
Registers Associated with Timer RC Interrupt
Timer RC Interrupt Block Diagram
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
IMIEC bit
IMIED bit
IMIEA bit
IMIEB bit
IMFC bit
IMFD bit
IMFA bit
IMFB bit
OVIE bit
OVF bit
Timer RC Interrupt Enable Register
TRCIER
Timer RC Interrupt Control Register
Timer RC interrupt request
(IR bit in TRCIC register)
TRCIC
19. Timer RC