R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 329

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 300 of 573
21.3
Table 21.2
Notes:
Transfer data format
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Selectable functions
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 21.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 21.3 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode.
1. When an external clock is selected, the requirements must be met in either of the following states:
2. If an overrun error occurs, the receive data (b0 to b8) in the U0RB register will be undefined.
- The external clock is held high when the CKPOL bit in the U0C0 register is set to 0 (transmit data
- The external clock is held low when the CKPOL bit in the U0C0 register is set to 1 (transmit data
The IR bit in the S0RIC register remains unchanged.
Clock Synchronous Serial I/O Mode
output at the falling edge and receive data input at the rising edge of the transfer clock)
output at the rising edge and receive data input at the falling edge of the transfer clock)
Item
Clock Synchronous Serial I/O Mode Specifications
• Transfer data length: 8 bits
• The CKDIR bit in the U0MR register is set to 0 (internal clock): fi/(2(n+1))
• The CKDIR bit is set to 1 (external clock): Input from the CLK0 pin
• To start transmission, the following requirements must be met:
• To start reception, the following requirements must be met:
• For transmission: One of the following can be selected.
• For reception:
• Overrun error
• CLK polarity selection
• LSB first, MSB first selection
• Continuous receive mode selection
fi = f1, f8, f32, fC n = setting value in the U0BRG register: 00h to FFh
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data present in the U0TB
- The RE bit in the U0C1 register is set to 1 (reception enabled).
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data present in the U0TB
- The U0IRS bit is set to 0 (transmit buffer empty):
- The U0IRS bit is set to 1 (transmission completed):
When data is transferred from the UART0 receive register to the U0RB
register (at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data
before reading the U0RB register and receives the 7th bit of the next unit of
data.
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
Reception is enabled immediately by reading the U0RB register.
register).
register).
When data is transferred from the U0TB register to the UART0 transmit
register (at start of transmission).
When data transmission from the UART0 transmit register is completed.
(2)
Specification
21. Serial Interface (UART0)
(1)
(1)