R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 332

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 303 of 573
Figure 21.3
• Transmit Timing Example (Internal Clock Selected)
• Receive Timing Example (External Clock Selected)
S0RIC register
S0TIC register
Transfer clock
U0C1 register
U0C1 register
U0C0 register
U0C1 register
U0C1 register
U0C1 register
U0C1 register
TXEPT bit in
The above applies when:
The above applies when:
The following should be met when “H” is applied to the CLK0 pin before receiving data:
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
• U0IRS bit in U0C1 register = 0
fEXT: Frequency of external clock
receive data input at the rising edge of the transfer clock)
(interrupt request generation when the transmit buffer is empty)
RE bit in
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
• TE bit in U0C1 register = 1 (transmission enabled)
• RE bit in U0C1 register = 1 (reception enabled)
• Dummy data is written to U0TB register
TE bit in
TE bit in
IR bit in
RI bit in
IR bit in
TI bit in
TI bit in
receive data input at the rising edge of the transfer clock)
RXD0
TXD0
CLK0
CLK0
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data is set in U0TB register.
Dummy data is set in U0TB register.
Data transfer from UART0 receive register
Data transfer from U0TB register to UART0 transmit register
Data transfer from U0TB register to UART0 transmit register
D0
D0
D1
D1
D2 D3
D2 D3
TCLK
to U0RB register
1/fEXT
D4
D4
TC
Receive data taken in
D5
D5
D6 D7
D6
Set to 0 by an interrupt request acknowledgement or by a program.
D7
D0 D1
Set to 0 when an interrupt request is acknowledged or by a program.
D0 D1
D2 D3
D2
Data read from U0RB register
D3
D4 D5
D4
D6
D5
TC = TCLK = 2(n+1)/fi
D7
fi: Frequency of U0BRG count source (f1, f8, f32, fC)
n: Setting value in U0BRG register
Pulsing stops because TE bit is set to 0.
D0 D1
21. Serial Interface (UART0)
D2 D3
D4 D5
D6
D7