R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 336

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 307 of 573
21.4
Table 21.5
Notes:
Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 21.5 lists the UART Mode Specifications. Table 21.6 lists the Registers Used and Settings in UART Mode.
1. If an overrun error occurs, the receive data (b0 to b8) in the U0RB register will be undefined.
2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UART0
The IR bit in the S0RIC register remains unchanged.
receive register to the U0RB register.
Clock Asynchronous Serial I/O (UART) Mode
Item
UART Mode Specifications
• Character bits (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bits: Selectable among 1 or 2 bits
• The CKDIR bit in the U0MR register is set to 0 (internal clock): fj/(16(n+1))
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
• To start transmission, the following requirements must be met:
• To start reception, the following requirements must be met:
• For transmission: One of the following can be selected.
• For reception:
• Overrun error
• Framing error
• Parity error
• Error sum flag
fj = f1, f8, f32, fC n = setting value in the U0BRG register: 00h to FFh
fEXT: Input from the CLK0 pin,
n = setting value in the U0BRG register: 00h to FFh
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data present in the U0TB
- The RE bit in the U0C1 register is set to 1 (reception enabled).
- Start bit detection
- The U0IRS bit is set to 0 (transmit buffer empty):
- The U0IRS bit is set to 1 (transfer completed):
When data is transferred from the UART0 receive register to the U0RB
register (at completion of reception).
This error occurs if the serial interface starts receiving the next unit of data
before reading the U0RB register and receive the bit one before the last
stop bit of the next unit of data.
This error occurs when the set number of stop bits is not detected.
This error occurs when parity is enabled, and the number of 1’s in the
parity and character bits do not match the set number of 1’s.
This flag is set to 1 if an overrun, framing, or parity error occurs.
When data is transferred from the U0TB register to the UART0 transmit
register (at start of transmission).
When data transmission from the UART0 transmit register is completed.
register).
(1)
Specification
21. Serial Interface (UART0)
(2)
(2)