R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 339

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 310 of 573
Figure 21.6
• Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)
• Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits)
S0TIC register
S0TIC register
Transfer clock
Transfer clock
U0C1 register
U0C1 register
U0C0 register
U0C1 register
U0C1 register
U0C0 register
TXEPT bit in
TXEPT bit in
TE bit in
TE bit in
IR bit in
IR bit in
TI bit in
TI bit in
TXD0
TXD0
The above applies when:
The above applies when:
• PRYE bit in U0MR register = 1 (parity enabled)
• STPS bit in U0MR register = 0 (one stop bit)
• U0IRS bit in U0C1 register = 1
• PRYE bit in U0MR register = 0 (parity disabled)
• STPS bit in U0MR register = 1 (two stop bits)
• U0IRS bit in U0C1 register = 0
(interrupt request generation when transmission is completed)
(interrupt request generation when the transmit buffer is empty)
Transmit Timing in UART Mode
Data is set in U0TB register.
Start
Data transfer from U0TB register to
UART0 transmit register
Start
Data is set in U0TB register.
Data transfer from U0TB register to
UART0 transmit register
bit
bit
ST
ST
D0
D0
D1
D1
TC
TC
D2
D2
D3
D3
Set to 0 when an interrupt request is acknowledged or by a program.
D4
D4
D5
D5
D6
D6
D7
D7 D8
Parity
bit
P
Stop
Stop
SP
bit
bit
SP SP
Stop
bit
ST
ST
D0
Set to 0 when an interrupt request is acknowledged or by a program.
D1
D0 D1
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
D2
fj: Frequency of U0BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U0BRG count source (external clock)
n: Setting value in U0BRG register
fj: Frequency of U0BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U0BRG count source (external clock)
n: Setting value in U0BRG register
D2 D3
D3
D4
D4
D5
D5
D6
D7
D6
Pulsing stops because TE bit is set to 0.
21. Serial Interface (UART0)
D7
P
D8
SP
SP SP
ST
D0 D1
ST
D0
D1

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