R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 358

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 329 of 573
Figure 22.3
(1) Transmit Timing Example (Internal Clock Selected)
(2) Receive Timing Example (External Clock Selected)
The above applies when:
The above applies when:
fEXT: Frequency of external clock
S2RIC register
U2RB register
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
U2C1 register
U2C1 register
U2C1 register
U2C1 register
• CKDIR bit in U2MR register = 0 (internal clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
• CKDIR bit in U2MR register = 1 (external clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
OER flag in
receive data input at the rising edge of the transfer clock)
S2TIC register
Transfer clock
U2C1 register
U2C1 register
TXEPT flag in
U2C0 register
RE bit in
TE bit in
RI bit in
IR bit in
TI bit in
RXD2
RTS2
CLK2
TE bit in
IR bit in
TI bit in
CTS2
CLK2
TXD2
Data transfer from UART2 receive
register to U2RB register
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data is set in U2TB register.
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Dummy data is set in U2TB register.
Data transfer from U2TB register to UART2 transmit register
Set to 0 when an interrupt request is acknowledged or by a program.
TCLK
1/fEXT
Received data taken in
TC
Data transfer from U2TB register to UART2 transmit register
Data read from U2RB register
Pulsing stops because “H” is applied
to CTS2.
D0 D1 D2 D3 D4 D5
Set to 0 when an interrupt request is acknowledged or by a program.
“L” is applied when U2RB register is read.
D0 D1 D2 D3 D4 D5 D6 D7
D6
D7
Make sure the following conditions are met
when the CLK2 pin input before receiving data is high:
• TE bit in U2C0 register = 1 (transmission enabled)
• RE bit in U2C1 register = 1 (reception enabled)
• Dummy data is written to U2TB register
D0 D1 D2 D3 D4 D5
TC = TCLK = 2(n+1)/fj
Pulsing stops because TE bit is set to 0.
fj: Frequency of U2BRG count source
n: Setting value in U2BRG register
D0 D1 D2 D3 D4 D5 D6 D7
(f1, f8, f32, fC)
22. Serial Interface (UART2)
D6