R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 372

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 343 of 573
Table 22.10
Note:
U2TB
U2RB
U2BRG
U2MR
U2C0
U2C1
U2SMR
U2SMR2 IICM2
Register
1. Set the bits not listed in this table to 0 when writing to the above registers in I
(1)
(1)
(1)
b0 to b7
b0 to b7
b8
OER
b0 to b7
SMD2 to SMD0 Set to 010b.
CKDIR
IOPOL
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
IICM
BBS
b3 to b7
CSC
SWC
STAC
SWC2
SDHI
b7
Registers Used and Settings in I
Bit
Set transmit data.
Receive data can be read.
ACK or NACK is set in this bit.
Overrun error flag
Set a bit rate.
Set to 0.
Set to 0.
Select the count source for the U2BRG
register.
Disabled because CRD = 1.
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Set to 1.
Set to 0.
Set to 1.
Bus busy flag
Set to 0.
Refer to Table 22.12 I
Functions .
Set to 1 to enable clock synchronization.
Set to 1 to fix SCL2 output low at the falling
edge of the 9th bit of clock.
Set to 0.
Set to 1 to forcibly pull SCL2 low.
Set to 1 to disable SDA2 output.
Set to 0.
Master
2
C Mode
2
C Mode (1)
Function
Set transmit data.
Receive data can be read.
ACK or NACK is set in this bit.
Overrun error flag
Disabled
Set to 010b.
Set to 1.
Set to 0.
Disabled
Disabled because CRD = 1.
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Set to 1.
Set to 0.
Set to 1.
Bus busy flag
Set to 0.
Refer to Table 22.12 I
Functions .
Set to 0.
Set to 1 to fix SCL2 output low at the falling
edge of the 9th bit of clock.
Set to 1 to initialize UART2 at start
condition detection
Set to 1 to forcibly pull SCL2 output low.
Set to 1 to disable SDA2 output.
Set to 0.
2
C mode.
22. Serial Interface (UART2)
Slave
2
C Mode