R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 393

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 364 of 573
24.2.3
Note:
24.2.4
Note:
b15 to b0
After Reset
1. Do not write to bits BS0 to BS3 during SSU operation.
Bits BS0 to BS3 (SSU Data Transfer Length Set Bit)
After Reset
After Reset
1. When the SSU data transfer length is set to 9 bits or more with the SSBR register, access the SSTDR register in
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 0193h
Address 0195h to 0194h
To set the SSBR register, set the RE bit in the SSER register to 0 (reception disabled) and the TE bit to 0
(transmission disabled).
As the SSU data transfer length, 8 to 16 bits can be used.
16-bit units.
Symbol
Symbol
Symbol
Symbol
Bit
Bit
Bit
BS0
BS1
BS2
BS3
SS Bit Counter Register (SSBR)
SS Transmit Data Register (SSTDR)
Symbol
b15
b7
b7
1
1
1
SSU data transfer length set bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is
started when it is detected that the SSTRSR register is empty.
When the next transmit data is written to the SSTDR register during the data
transmission from the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data with LSB-first), the data
in which MSB and LSB are reversed is read, after writing to the SSTDR register.
b14
b6
b6
1
1
1
Bit Name
b13
b5
b5
1
1
1
(1)
b12
b4
b4
1
1
1
(1)
b3 b2 b1 b0
0 0 0 0: 16 bits
1 0 0 0: 8 bits
1 0 0 1: 9 bits
1 0 1 0: 10 bits
1 0 1 1: 11 bits
1 1 0 0: 12 bits
1 1 0 1: 13 bits
1 1 1 0: 14 bits
1 1 1 1: 15 bits
BS3
b11
b3
b3
Function
1
1
1
24. Synchronous Serial Communication Unit (SSU)
BS2
b10
b2
b2
0
1
1
Function
BS1
b1
b1
b9
0
1
1
BS0
b0
b0
b8
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W

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