R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 396

MCU 1KB FLASH 16K ROM 20-LSSOP

R5F21324CNSP#U0

Manufacturer Part Number
R5F21324CNSP#U0
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Cr
Datasheet

Specifications of R5F21324CNSP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 367 of 573
24.2.8
Note:
After Reset
1. Refer to 24.3.1.1 Association between Transfer Clock Polarity, Phase, and Data for the settings of the CPHS
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ah
and CPOS bits.
When the SSUMS bit in the SSMR2 register is set to 0 (clock synchronous communication mode), set the CPHS
bit to 0 and the CPOS bit to 0.
Symbol
Symbol
CPOS
Bit
CPHS
MLS
BC0
BC1
BC2
BC3
SS Mode Register (SSMR)
MLS
b7
0
Bits counter 3 to 0
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
SSCK clock phase select bit
SSCK clock polarity select bit
MSB first/LSB first select bit
CPOS
b6
0
Bit Name
CPHS
b5
0
(1)
(1)
b4
1
b3 b2 b1 b0
0: Change data at odd edge
1: Change data at even edge
0: “H” when clock stops
1: “L” when clock stops
0: Transfers data MSB first
1: Transfers data LSB first
0 0 0 0: 16 bits left
0 0 0 1: 1 bit left
0 0 1 0: 2 bits left
0 0 1 1: 3 bits left
0 1 0 0: 4 bits left
0 1 0 1: 5 bits left
0 1 1 0: 6 bits left
0 1 1 1: 7 bits left
1 0 0 0: 8 bits left
1 0 0 1: 9 bits left
1 0 1 0: 10 bits left
1 0 1 1: 11 bits left
1 1 0 0: 12 bits left
1 1 0 1: 13 bits left
1 1 1 0: 14 bits left
1 1 1 1: 15 bits left
BC3
b3
(Download data at even edge)
(Download data at odd edge)
0
24. Synchronous Serial Communication Unit (SSU)
BC2
b2
0
Function
BC1
b1
0
BC0
b0
0
R/W
R/W
R/W
R/W
R
R
R
R

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