R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 449

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 420 of 573
Figure 25.15
25.5.3
Program processing
MST bit in ICCR1
RDRF bit in ICSR
TRS bit in ICCR1
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 25.15 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits CKS0 to CKS3 in the
(2) Set the MST bit to 1 while the transfer clock is being output. This will start the output of the receive clock.
(3) When the receive operation is completed, data is transferred from registers ICDRS to ICDRR and the
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (next receive operation disabled)
ICDRS register
ICDRR register
ICCR1 register and the MST bit (initial setting).
RDRF bit in the ICSR register is set to 1. When the MST bit is set to 1, the clock is output continuously
since the next byte of data is enabled for reception. Continuous reception is enabled by reading the ICDRR
register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is set to 1, an
overrun is detected and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
and read the ICDRR register. The SCL signal is fixed “H” after the following byte of data reception is
completed.
register
register 0
register
Receive Operation
(input)
SDA
SCL
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
(2) Set MST bit to 1
(when transfer clock is output).
b0
1
b1
Data 1
2
(3) Read ICDRR register.
b6
7
b7
8
b0
Data 1
1
Data 2
b6
7
(3) Read ICDRR register.
b7
8
Data 2
25. I
1
2
C bus Interface
b0
Data 3
2