R5F21324CNSP#U0 Renesas Electronics America, R5F21324CNSP#U0 Datasheet - Page 80

• Manufacturer Part Number: R5F21324CNSP#U0
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Cr

Specifications of R5F21324CNSP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/32C Group
REJ09B0573-0100 Rev.1.00 Dec. 18, 2009
Page 51 of 573
6.5
Table 6.2
Notes:
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an
Operating Example of Voltage Monitor 1 Interrupt.
To use the voltage monitor 1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter
disabled).
12
Step
5
7
1. When the VW1C0 bit is set to 0, steps 4 and 5 can be executed simultaneously (with one instruction).
2. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed simultaneously (with one instruction).
3. When making the setting while the voltage monitor 1 interrupt is disabled (the VW1C0 bit in the
10
11
1
2
3
4
6
8
9
(2)
(1)
(3)
VW1C register is 0 and the VCA26 bit in the VCA2 register is 0), no interrupt request is generated if
VCC < Vdet1 (or VCC > Vdet1) is detected before enabling the voltage monitor 1 interrupt in step 12.
If VCC < Vdet1 (or VCC > Vdet1) is detected between step 10 and step 12, the VW1C2 bit is set to 1.
Read the VW1C2 bit after step 12. If this bit is read as 1, perform the processing to be executed when
the above state is detected.
Voltage Monitor 1 Interrupt
Select the voltage detection 1 detection voltage by bits VD1S3 to VD1S0 in the VD1LS register.
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled).
Wait for td(E-A).
Set the COMPSEL bit in the CMPA register to 1.
Select the interrupt type by the IRQ1SEL in the CMPA register.
Select the sampling clock of the digital filter by
bits VW1F0 and VW1F1 in the VW1C register.
Set the VW1C1 bit in the VW1C register to 0
(digital filter enabled).
Select the interrupt request timing by the VCAC1 bit in the VCAC register and
the VW1C7 bit in the VW1C register.
Set the VW1C2 bit in the VW1C register to 0.
Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
Wait for 2 cycles of the sampling clock of
the digital filter
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt enabled)
Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt
When Using Digital Filter
Set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
−
−
− (No wait time required)
When Using No Digital Filter
6. Voltage Detection Circuit