R5F21292SNSP#U0 Renesas Electronics America, R5F21292SNSP#U0 Datasheet
R5F21292SNSP#U0
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R5F21292SNSP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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R8C/28 Group, 16 R8C/29 Group Hardware Manual RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 XXX4 XXX5 XXX6 XXX7 *1 Blank: Set ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. All trademarks and ...
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SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Applications ............................................................................................................................................... 1 1.2 Performance Overview .............................................................................................................................. 2 1.3 Block Diagram .......................................................................................................................................... 4 1.4 Product Information .................................................................................................................................. 5 1.5 Pin Assignments ........................................................................................................................................ 7 1.6 Pin Functions ............................................................................................................................................. 8 ...
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Voltage Detection Circuit .............................................................................................................. 32 6.1 VCC Input Voltage .................................................................................................................................. 43 6.1.1 Monitoring Vdet0 ............................................................................................................................... 43 6.1.2 Monitoring Vdet1 ............................................................................................................................... 43 6.1.3 Monitoring Vdet2 ............................................................................................................................... 43 6.2 Voltage Monitor 0 Reset (For N, D Version only) .................................................................................. 44 6.3 ...
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Protection .................................................................................................................................... 102 12. Interrupts ..................................................................................................................................... 103 12.1 Interrupt Overview ................................................................................................................................ 103 12.1.1 Types of Interrupts ............................................................................................................................ 103 12.1.2 Software Interrupts ........................................................................................................................... 104 12.1.3 Special Interrupts .............................................................................................................................. 105 12.1.4 Peripheral Function Interrupt ............................................................................................................ 105 12.1.5 Interrupts and Interrupt Vectors ...
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PWM2 Mode ..................................................................................................................................... 207 14.3.8 Timer RC Interrupt ........................................................................................................................... 213 14.3.9 Notes on Timer RC ........................................................................................................................... 214 14.4 Timer RE ............................................................................................................................................... 215 14.4.1 Real-Time Clock Mode (For N, D Version Only) ............................................................................ 216 14.4.2 Output Compare Mode ..................................................................................................................... 224 ...
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A/D Converter ............................................................................................................................. 328 18.1 One-Shot Mode ..................................................................................................................................... 332 18.2 Repeat Mode .......................................................................................................................................... 334 18.3 Sample and Hold ................................................................................................................................... 336 18.4 A/D Conversion Cycles ......................................................................................................................... 336 18.5 Internal Equivalent Circuit of Analog Input .......................................................................................... 337 18.6 Output Impedance of ...
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Notes on Serial Interface ....................................................................................................................... 428 21.5 Notes on Clock Synchronous Serial Interface ....................................................................................... 429 21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 429 2 21.5.2 Notes bus Interface ................................................................................................................ 429 21.6 Notes ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h 0009h 000Ah Protect Register 000Bh 000Ch Oscillation Stop ...
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Address Register 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h ...
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Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h 0106h LIN Control Register 0107h LIN Status Register 0108h Timer RB Control ...
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Address Register 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h ...
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R8C/28 Group, R8C/29 Group SINGLE-CHIP 16-BIT CMOS MCU 1. Overview These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C CPU core, and are packaged in a 20-pin molded-plastic LSSOP. It implements sophisticated instructions for a ...
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R8C/28 Group, R8C/29 Group 1.2 Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/28 Group and Table 1.2 outlines the Functions and Specifications for R8C/29 Group. Table 1.1 Functions and Specifications for R8C/28 Group Item CPU Number of ...
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R8C/28 Group, R8C/29 Group Table 1.2 Functions and Specifications for R8C/29 Group Item CPU Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Peripheral Ports Functions LED drive ports Timers Serial interfaces Clock synchronous serial ...
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R8C/28 Group, R8C/29 Group 1.3 Block Diagram Figure 1.1 shows a Block Diagram. I/O ports Peripheral functions Timers Timer RA (8 bits) Timer RB (8 bits) Timer RC (16 bits × 1 channel) Timer RE (8 bits) Watchdog timer (15 ...
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R8C/28 Group, R8C/29 Group 1.4 Product Information Table 1.3 lists the Product Information for R8C/28 Group and Table 1.4 lists the Product Information for R8C/29 Group. Table 1.3 Product Information for R8C/28 Group Type No. R5F21282SNSP R5F21284SNSP R5F21282SDSP R5F21284SDSP R5F21284JSP ...
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R8C/28 Group, R8C/29 Group Table 1.4 Product Information for R8C/29 Group Type No. Program ROM R5F21292SNSP 8 Kbytes 1 Kbyte × 2 512 bytes PLSP0020JB-A N version R5F21294SNSP 16 Kbytes 1 Kbyte × Kbyte R5F21292SDSP 8 Kbytes 1 ...
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R8C/28 Group, R8C/29 Group 1.5 Pin Assignments Figure 1.4 shows Pin Assignments (Top View). P3_5/SCL/SSCK/TRCIOD (2) P3_7/TRAO/SSO/RXD1/(TXD1) RESET (1, 3) XOUT/XCOUT/P4_7 VSS/AVSS (3) XIN/XCIN/P4_6 VCC/AVCC MODE (2) P4_5/INT0/(RXD1) P1_7/TRAIO/INT1 NOTES: 1. P4_7 is an input-only port. 2. Can be assigned ...
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R8C/28 Group, R8C/29 Group 1.6 Pin Functions Table 1.5 lists Pin Functions. Table 1.5 Pin Functions Type Symbol Power supply input VCC, VSS Analog power AVCC, AVSS supply input Reset input RESET MODE MODE XIN clock input XIN XIN clock ...
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R8C/28 Group, R8C/29 Group Table 1.6 Pin Name Information by Pin Number Pin Control Pin Port Number 1 P3_5 2 P3_7 3 RESET XOUT/ 4 P4_7 (2) XCOUT 5 VSS/AVSS (2) 6 P4_6 XIN/XCIN 7 VCC/AVCC 8 MODE 9 P4_5 ...
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R8C/28 Group, R8C/29 Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 ...
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R8C/28 Group, R8C/29 Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bits (R0H) and low-order ...
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R8C/28 Group, R8C/29 Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag ...
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R8C/28 Group, R8C/29 Group 3. Memory 3.1 R8C/28 Group Figure 3 Memory Map of R8C/28 Group. The R8C/28 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning ...
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R8C/28 Group, R8C/29 Group 3.2 R8C/29 Group Figure 3 Memory Map of R8C/29 Group. The R8C/29 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning ...
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R8C/28 Group, R8C/29 Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h ...
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R8C/28 Group, R8C/29 Group Table 4.2 SFR Information (2) Address 0030h 0031h Voltage Detection Register 1 0032h Voltage Detection Register 2 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register 0037h Voltage Monitor 2 Circuit Control Register 0038h Voltage ...
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R8C/28 Group, R8C/29 Group Table 4.3 SFR Information (3) Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh ...
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R8C/28 Group, R8C/29 Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2 00D5h 00D6h A/D ...
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R8C/28 Group, R8C/29 Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h 0106h LIN Control Register ...
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R8C/28 Group, R8C/29 Group Table 4.6 SFR Information (6) Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh ...
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R8C/28 Group, R8C/29 Group Table 4.7 SFR Information (7) Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh ...
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R8C/28 Group, R8C/29 Group 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset (for N, D version only), voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 ...
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R8C/28 Group, R8C/29 Group RESET Power-on reset VCC Voltage detection Watchdog Figure 5.2 Block Diagram of Reset Circuit (J, K Version) Rev.2.10 Sep 26, 2008 Page 23 of 441 REJ09B0279-0210 Hardware reset Power-on reset circuit Voltage monitor 0 reset Voltage ...
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R8C/28 Group, R8C/29 Group Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.3 shows the CPU Register Status after Reset, Figure 5.4 shows the Reset Sequence, and Figure 5.5 shows the OFS Register. Table 5.2 ...
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R8C/28 Group, R8C/29 Group Option Function Select Register Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) LVD0ON LVD1ON CSPROINI NOTES: 1. The OFS register is on the ...
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R8C/28 Group, R8C/29 Group 5.1 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all ...
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R8C/28 Group, R8C/29 Group VCC RESET Figure 5.6 Example of Hardware Reset Circuit and Operation RESET Figure 5.7 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation Rev.2.10 Sep 26, 2008 Page 27 of ...
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R8C/28 Group, R8C/29 Group 5.2 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset ...
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R8C/28 Group, R8C/29 Group VCC 4.7 kΩ (reference) RESET (3) V det1 External power por1 t w(por1) Internal reset signal (“L” valid) NOTES: 1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V ...
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R8C/28 Group, R8C/29 Group 5.3 Voltage Monitor 0 Reset (N, D Version) A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor ...
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R8C/28 Group, R8C/29 Group 5.6 Voltage Monitor 2 Reset A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet2. When ...
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R8C/28 Group, R8C/29 Group 6. Voltage Detection Circuit The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 0 reset (for ...
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R8C/28 Group, R8C/29 Group Table 6.2 Specifications of Voltage Detection Circuit (J, K Version) Item VCC Monitor Voltage to monitor Detection target Monitor Process Reset When Voltage is Detected Interrupt Digital Filter Switch enabled/disabled Sampling time VCC Internal reference voltage ...
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R8C/28 Group, R8C/29 Group VCC Internal reference voltage Figure 6.2 Block Diagram of Voltage Detection Circuit (J, K Version) Voltage detection 0 circuit VCA25 VCC + Internal - reference voltage Voltage detection 0 signal is held “H” when VCA25 bit ...
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R8C/28 Group, R8C/29 Group Voltage detection 1 circuit fOCO-S VCA26 VCC + Noise filter Voltage Internal - detection reference 1 signal (Filter width: 200 ns) voltage Voltage detection 1 signal is held “H” when VCA26 bit is set to 0 ...
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R8C/28 Group, R8C/29 Group Voltage detection 2 circuit fOCO-S VCA27 VCA13 VCC + Noise filter Voltage Internal - detection reference 2 signal (Filter width: 200 ns) voltage Voltage detection 2 signal is held “H” when VCA27 bit is set to ...
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R8C/28 Group, R8C/29 Group Voltage Detection Register Symbol VCA1 Bit Symbol — (b2-b0) VCA13 — (b7-b4) NOTES: 1. The VCA13 bit is enabled w ...
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R8C/28 Group, R8C/29 Group Voltage Detection Register Symbol VCA2 Bit Symbol VCA20 — (b5-b1) VCA26 VCA27 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/28 Group, R8C/29 Group Voltage Monitor 0 Circuit Control Register Symbol VW0C Bit Symbol VW0C0 VW0C1 VW0C2 — (b3) VW0F0 VW0F1 VW0C6 VW0C7 NOTES: 1. Set the PRC3 bit in the ...
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R8C/28 Group, R8C/29 Group Voltage Monitor 1 Circuit Control Register Symbol VW1C Bit Symbol VW1C0 VW1C1 VW1C2 VW1C3 VW1F0 VW1F1 VW1C6 VW1C7 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/28 Group, R8C/29 Group Voltage Monitor 1 Circuit Control Register Symbol VW1C Bit Symbol VW1C0 VW1C1 — (b2) — (b3) VW1F0 VW1F1 VW1C6 VW1C7 NOTES: 1. Set the PRC3 bit in ...
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R8C/28 Group, R8C/29 Group Voltage Monitor 2 Circuit Control Register Symbol VW2C Bit Symbol VW2C0 VW2C1 VW2C2 VW2C3 VW2F0 VW2F1 VW2C6 VW2C7 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/28 Group, R8C/29 Group 6.1 VCC Input Voltage 6.1.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.1.2 Monitoring Vdet1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed (refer to 20. ...
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R8C/28 Group, R8C/29 Group 6.2 Voltage Monitor 0 Reset (For N, D Version only) Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.13 shows an Example of Voltage Monitor 0 Reset Operation. To ...
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R8C/28 Group, R8C/29 Group 6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset (N, D Version) Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.14 shows an Example of Voltage ...
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R8C/28 Group, R8C/29 Group Vdet1 (1) 2.2 V VW1C3 bit VW1C2 bit When the VW1C1 bit is set to 0 (digital filter enabled) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) VW1C2 bit When ...
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R8C/28 Group, R8C/29 Group 6.4 Voltage Monitor 1 Reset (J, K Version) Table 6.5 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Reset. Figure 6.15 shows an Example of Voltage Monitor 1 Reset Operation (J, K Version). ...
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R8C/28 Group, R8C/29 Group 6.5 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Table 6.6 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.16 shows an Example of Voltage Monitor 2 Interrupt ...
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R8C/28 Group, R8C/29 Group Vdet2 (1) 2.2 V VCA13 bit VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) VW2C2 bit When ...
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R8C/28 Group, R8C/29 Group 7. Programmable I/O Ports There are 13 programmable Input/Output ports (I/O ports) P1, P3_3 to P3_5, P3_7, and P4_5. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit and ...
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R8C/28 Group, R8C/29 Group 7.2 Effect on Peripheral Functions Programmable I/O ports function as I/O ports for peripheral functions (refer to Table 1.6 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as ...
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R8C/28 Group, R8C/29 Group P1_0 to P1_3 Direction register Output from individual peripheral function Data bus Port latch Input to individual peripheral function P1_4 Direction register Output from individual peripheral function Data bus Port latch NOTE: 1. symbolizes a parasitic ...
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R8C/28 Group, R8C/29 Group P1_5 and P1_7 Direction register Output from individual peripheral function Port latch Data bus Input to external interrupt Input to individual peripheral function P1_6 Direction register Output from individual peripheral function Data bus Port latch Input ...
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R8C/28 Group, R8C/29 Group P3_3 Output from individual peripheral function Data bus Input to individual peripheral function Input to external interrupt P3_4, P3_5, and P3_7 Output from individual peripheral function Data bus Input to individual peripheral function NOTE: 1. Ensure ...
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R8C/28 Group, R8C/29 Group P4_2/VREF P4_5 Data bus Input to individual peripheral function (N, D Version) P4_6/XIN Data bus P4_7/XOUT Data bus (J, K Version) P4_6/XIN Data bus P4_7/XOUT Data bus NOTES: 1. Ensure the input voltage to each port ...
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R8C/28 Group, R8C/29 Group MODE MODE signal input RESET RESET signal input NOTE: 1. Ensure the input voltage to each port does not exceed VCC. Figure 7.5 Configuration of I/O Pins Rev.2.10 Sep 26, 2008 Page 56 of 441 REJ09B0279-0210 ...
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R8C/28 Group, R8C/29 Group Port Pi Direction Register ( Symbol PD1 PD3 PD4 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 NOTES: 1. Bits PD3_0 to ...
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R8C/28 Group, R8C/29 Group Pin Select Register Symbol PINSR1 Bit Symbol UART1SEL0 UART1SEL1 — (b2) — (b7-b3) NOTE: 1. The UART1 pins can be selected ...
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R8C/28 Group, R8C/29 Group Port Mode Register Symbol PMR Bit Symbol — (b0) — (b2-b1) SSISEL U1PINSEL TXD1SEL TXD1EN IICSEL NOTE: 1. The UART1 pins can be selected by using bits ...
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R8C/28 Group, R8C/29 Group Pull-Up Control Register Symbol PUR0 Bit Symbol — (b1-b0) PU02 PU03 — (b5-b4) PU06 PU07 NOTE: 1. When this bit is set to ...
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R8C/28 Group, R8C/29 Group 7.4 Port Settings Tables 7.4 to 7.25 list the port settings. Table 7.4 Port P1_0/KI0/AN8 Register PD1 KIEN Bit PD1_0 KI0EN Setting Value NOTE: ...
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R8C/28 Group, R8C/29 Group Table 7.8 TRCIOB Pin Setting Register TRCOER Bit EB PWM2 Setting Value Table 7.9 Port P1_3/KI3/AN11/TRBO Register PD1 KIEN Bit PD1_3 KI3EN 0 ...
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R8C/28 Group, R8C/29 Group Table 7.12 Port P1_5/RXD0/(TRAIO)/(INT1) Register PD1 TRAIOC Bit PD1_5 TIOSEL Setting 1 Value NOTES: 1. Pulled up ...
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R8C/28 Group, R8C/29 Group Table 7.15 Port P3_3/INT3/SSI/TRCCLK Clock Synchronous Serial I/O with Chip Register PD3 PMR Communication Modes and I/O Pins.) Bit PD3_3 IICSEL SSI output control Setting Value ...
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R8C/28 Group, R8C/29 Group Table 7.18 Port P3_5/SCL/SSCK/TRCIOD Register PD3 PMR ICCR1 Bit PD3_5 IICSEL ICE Setting X X Value NOTES: 1. ...
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R8C/28 Group, R8C/29 Group Table 7.20 Port P3_7/TRAO/SSO/RXD1/(TXD1) Clock Synchronous Serial I/O with Chip Register PD3 PMR Communication Modes and I/O Pins.) Bit PD3_7 IICSEL SSO output control Setting Value ...
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R8C/28 Group, R8C/29 Group Table 7.22 Port P4_2/VREF Register ADCON1 Bit VCUT 0 Setting Value 1 Table 7.23 Port P4_5/INT0/(RXD1) Register PD4 Bit PD4_5 0 1 Setting Value 0 0 NOTES: 1. Pulled up by setting the PU11 bit in ...
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R8C/28 Group, R8C/29 Group Table 7.25 Port P4_7/XOUT/XCOUT Register CM0 Bit CM01 CM04 CM05 Setting Value NOTES: 1. Since the XCIN-XCOUT oscillation buffer operates with ...
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R8C/28 Group, R8C/29 Group 7.5 Unassigned Pin Handling Table 7.26 lists the Unassigned Pin Handling. Table 7.26 Unassigned Pin Handling Pin Name Ports P1, P3_3 to P3_5, P3_7, P4_5 Ports P4_6, P4_7 Port P4_2/VREF (3) RESET NOTES these ...
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R8C/28 Group, R8C/29 Group 8. Processor Mode 8.1 Processor Modes Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table ...
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R8C/28 Group, R8C/29 Group 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/28 Group and Table 9.2 lists Bus Cycles by Access Space of the ...
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R8C/28 Group, R8C/29 Group 10. Clock Generation Circuit The clock generation circuit has: • XIN clock oscillation circuit • XCIN clock oscillation circuit (For N, D version only) • Low-speed on-chip oscillator • High-speed on-chip oscillator However, use one of ...
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R8C/28 Group, R8C/29 Group Stop signal (1) XOUT/XCOUT (1) XIN/XCIN CM01 = 0 CM13 CM05 CM04 XIN CM01 clock XCIN clock S Q CM10 = 1 (stop mode) R RESET Power-on reset Software reset Interrupt request S Q WAIT instruction ...
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R8C/28 Group, R8C/29 Group System Clock Control Register Symbol CM0 Bit Symbol — (b0) CM01 CM02 CM03 CM04 CM05 CM06 — (b7) NOTES: 1. Set the PRC0 bit in ...
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R8C/28 Group, R8C/29 Group System Clock Control Register Symbol CM1 Bit Symbol CM10 CM11 CM12 CM13 CM14 CM15 CM16 CM17 NOTES: 1. Set the PRC0 bit in the PRCR register to ...
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R8C/28 Group, R8C/29 Group Oscillation Stop Detection Register Symbol OCD Bit Symbol OCD0 OCD1 OCD2 OCD3 — (b7-b4) NOTES: 1. Set the PRC0 bit in the PRCR register ...
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R8C/28 Group, R8C/29 Group High-Speed On-Chip Oscillator Control Register Symbol FRA0 Bit Symbol FRA00 FRA01 — (b7-b2) NOTES: Set the PRC0 bit in the PRCR ...
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R8C/28 Group, R8C/29 Group High-Speed On-Chip Oscillator Control Register Symbol FRA2 Bit Symbol FRA20 FRA21 FRA22 — (b7-b3) NOTES: 1. Set the PRC0 bit in the ...
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R8C/28 Group, R8C/29 Group Clock Prescaler Reset Flag (For N, D Version Only Symbol CPSRF Bit Symbol — (b6-b0) CPSR NOTE: 1. Only w rite ...
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R8C/28 Group, R8C/29 Group Voltage Detection Register Symbol VCA2 Bit Symbol VCA20 — (b5-b1) VCA26 VCA27 NOTES: 1. Set the PRC3 bit in the PRCR register ...
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R8C/28 Group, R8C/29 Group Handling procedure of internal power low consumption enabled by VCA20 bit Enter low-speed clock mode or low-speed on- Step (1) chip oscillator mode Stop XIN clock and high-speed on-chip Step (2) oscillator clock VCA20 ← 1 ...
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R8C/28 Group, R8C/29 Group The clocks generated by the clock generation circuits are described below. 10.1 XIN Clock This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and ...
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R8C/28 Group, R8C/29 Group 10.2 On-Chip Oscillator Clocks These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register. 10.2.1 Low-Speed ...
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R8C/28 Group, R8C/29 Group 10.3 XCIN Clock (For N, D Version Only) This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU clock, peripheral function clock. The XCIN clock ...
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R8C/28 Group, R8C/29 Group 10.4 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit. 10.4.1 System Clock ...
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R8C/28 Group, R8C/29 Group 10.4.8 fC4 and fC32 The clock fC4 is used for timer RE and the clock fC32 is used for timer RA. Use fC4 and fC32 while the XCIN clock oscillation stabilizes. (For J, K version, fC4 ...
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R8C/28 Group, R8C/29 Group 10.5 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 10.5.1 Standard Operating Mode Standard operating mode is further separated into ...
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R8C/28 Group, R8C/29 Group 10.5.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division provides the CPU clock. Set the CM06 bit to 1 (divide- by-8 mode) when transiting to high-speed on-chip oscillator ...
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R8C/28 Group, R8C/29 Group 10.5.2 Wait Mode Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, ...
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R8C/28 Group, R8C/29 Group 10.5.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or a peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral ...
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R8C/28 Group, R8C/29 Group Figure 10.13 shows the Time from Wait Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority ...
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R8C/28 Group, R8C/29 Group 10.5.2.5 Reducing Internal Power Consumption Internal power consumption can be reduced by using low-speed clock mode (for N, D version only) or low- speed on-chip oscillator mode. Figure 10.14 shows the Procedure for Enabling Reduced Internal ...
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R8C/28 Group, R8C/29 Group 10.5.3 Stop Mode Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to ...
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R8C/28 Group, R8C/29 Group 10.5.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 10.15 shows the Time from Stop Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit ...
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R8C/28 Group, R8C/29 Group Figure 10.16 shows the State Transitions in Power Control Mode (When the CM01 bit in the CM0 register is set to 0 (XIN clock)). Figure 10.17 shows the State Transitions in Power Control Mode (When the ...
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R8C/28 Group, R8C/29 Group State Transitions in Power Control Mode (When the CM01 bit in the CM0 register is set to 1 (XCIN clock)) (For N, D version only) Reset Low-speed on-chip oscillator mode CM14 = 0 OCD2 = 1 ...
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R8C/28 Group, R8C/29 Group 10.6 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD ...
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R8C/28 Group, R8C/29 Group Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts Generated Interrupt Source Oscillation stop detection ((a) or (b)) Watchdog timer (1) Voltage monitor 1 Voltage monitor ...
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R8C/28 Group, R8C/29 Group Interrupt sources judgement OCD3 = (XIN clock stopped) YES (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock) ? Set OCD1 bit to 0 (oscillation stop ...
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R8C/28 Group, R8C/29 Group Interrupt sources judgement OCD3 = 1 ? (XIN clock stopped) YES Set OCD1 bit to 0 (oscillation stop (1) detection interrupt disabled). To oscillation stop detection interrupt routine NOTE: 1. This disables multiple oscillation stop detection ...
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R8C/28 Group, R8C/29 Group 10.7 Notes on Clock Generation Circuit 10.7.1 Stop Mode When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to ...
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R8C/28 Group, R8C/29 Group 11. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. • ...
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R8C/28 Group, R8C/29 Group 12. Interrupts 12.1 Interrupt Overview 12.1.1 Types of Interrupts Figure 12.1 shows the Types of Interrupts. Software (non-maskable interrupts) Interrupts Hardware NOTES: 1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts. 2. ...
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R8C/28 Group, R8C/29 Group 12.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 12.1.2.1 Undefined Instruction Interrupt The undefined instruction interrupt is generated when the UND instruction is executed. 12.1.2.2 Overflow Interrupt ...
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R8C/28 Group, R8C/29 Group 12.1.3 Special Interrupts Special interrupts are non-maskable. 12.1.3.1 Watchdog Timer Interrupt The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer. 12.1.3.2 Oscillation Stop Detection Interrupt The oscillation stop ...
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R8C/28 Group, R8C/29 Group 12.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address ...
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R8C/28 Group, R8C/29 Group 12.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables Vector Addresses Interrupt ...
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R8C/28 Group, R8C/29 Group 12.1.6 Interrupt Control The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ...
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R8C/28 Group, R8C/29 Group (1) Interrupt Control Register TRCIC SSUIC/IICIC Bit Symbol ILVL0 ILVL1 ILVL2 IR — (b7-b4) NOTES: 1. Rew rite the interrupt control register w hen the interrupt request w ...
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R8C/28 Group, R8C/29 Group INTi Interrupt Control Register (i= Symbol INT1IC INT3IC INT0IC Bit Symbol ILVL0 ILVL1 ILVL2 IR POL — (b5) — (b7-b6) NOTES: 1. Only 0 can ...
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R8C/28 Group, R8C/29 Group 12.1.6.1 I Flag The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts. 12.1.6.2 IR Bit The ...
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R8C/28 Group, R8C/29 Group 12.1.6.4 Interrupt Sequence An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level ...
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R8C/28 Group, R8C/29 Group 12.1.6.5 Interrupt Response Time Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt ...
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R8C/28 Group, R8C/29 Group 12.1.6.7 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order ...
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R8C/28 Group, R8C/29 Group 12.1.6.8 Returning from an Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, ...
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R8C/28 Group, R8C/29 Group 12.1.6.10 Interrupt Priority Judgement Circuit The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11. Priority level of interrupt INT3 Timer RB Timer RA INT0 INT1 Timer RC UART1 receive UART0 ...
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R8C/28 Group, R8C/29 Group 12.2 INT Interrupt 12.2.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 ...
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R8C/28 Group, R8C/29 Group ______ INT0 Input Filter Select Register Symbol INTF Bit Symbol INT0F0 INT0F1 INT1F0 INT1F1 — (b5-b4) INT3F0 INT3F1 Figure 12.13 INTF Register Rev.2.10 Sep 26, 2008 ...
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R8C/28 Group, R8C/29 Group 12.2.2 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF register. The INTi level is sampled every ...
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R8C/28 Group, R8C/29 Group 12.3 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit ...
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R8C/28 Group, R8C/29 Group (1) Key Input Enable Register Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL NOTE: 1. The IR bit in the KUPIC register may be ...
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R8C/28 Group, R8C/29 Group 12.4 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register ( 1). This interrupt is used as a ...
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R8C/28 Group, R8C/29 Group Address Match Interrupt Enable Register Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address Match Interrupt Register (b23) (b19) (b16) (b15) b7 ...
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R8C/28 Group, R8C/29 Group 12.5 Timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I Request Sources) The timer RC interrupt, clock synchronous serial I/O with chip select interrupt, and I have multiple interrupt request sources. An ...
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R8C/28 Group, R8C/29 Group As with other maskable interrupts, the timer RC interrupt, clock synchronous serial I/O with chip select interrupt, 2 and I C bus interface interrupt are controlled by the combination of the I flag, IR bit, bits ...
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R8C/28 Group, R8C/29 Group 12.6 Notes on Interrupts 12.6.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h ...
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R8C/28 Group, R8C/29 Group 12.6.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt ...
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R8C/28 Group, R8C/29 Group 12.6.5 Changing Interrupt Control Register Contents (a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts ...
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R8C/28 Group, R8C/29 Group 13. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains ...
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R8C/28 Group, R8C/29 Group Option Function Select Register Symbol OFS Bit Symbol WDTON — (b1) ROMCR ROMCP1 — (b4) LVD0ON LVD1ON CSPROINI NOTES: 1. The OFS register is on the ...
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R8C/28 Group, R8C/29 Group Watchdog Timer Reset Register b7 b0 Symbol WDTR When 00h is w ritten before w riting FFh, the w atchdog timer is reset. The default value of the w atchdog timer is 7FFFh w hen count ...
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R8C/28 Group, R8C/29 Group 13.1 Count Source Protection Mode Disabled The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Specifications of Watchdog Timer (with Count Source Protection ...
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R8C/28 Group, R8C/29 Group 13.2 Count Source Protection Mode Enabled The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out ...
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R8C/28 Group, R8C/29 Group 14. Timers The microcomputer contains two 8-bit timers with 8-bit prescaler, a 16-bit timer, and a timer with a 4-bit counter, and an 8-bit counter. The two 8-bit timers with the 8-bit prescaler contain Timer RA ...
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R8C/28 Group, R8C/29 Group Table 14.1 Functional Comparison of Timers Item Configuration Count (1) Count source Function Timer Mode Pulse Output Mode Event Counter Mode Pulse Width Measurement Mode Pulse Period Measurement Mode Programmable Waveform Generation Mode Programmable One-Shot generation ...
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R8C/28 Group, R8C/29 Group 14.1 Timer RA Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, ...
Page 156
R8C/28 Group, R8C/29 Group (4) Timer RA Control Register Symbol TRACR Bit Symbol TSTART TCSTF TSTOP — (b3) TEDGF TUNDF — (b7-b6) NOTES: 1. Refer to 14.1.6 Notes on Tim er RA ...
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R8C/28 Group, R8C/29 Group Timer RA Mode Register Symbol TRAMR Bit Symbol TMOD0 TMOD1 TMOD2 — (b3) TCK0 TCK1 TCK2 TCKCUT NOTES: 1. When both the TSTART and TCSTF bits in the ...
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R8C/28 Group, R8C/29 Group 14.1.1 Timer Mode In this mode, the timer counts an internally generated count source (refer to Table 14.2 Specifications of Timer Mode). Figure 14.4 shows the TRAIOC Register in Timer Mode. Table 14.2 Specifications of Timer ...
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R8C/28 Group, R8C/29 Group 14.1.1.1 Timer Write Control during Count Operation Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to ...
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R8C/28 Group, R8C/29 Group 14.1.2 Pulse Output Mode In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 14.3 ...
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R8C/28 Group, R8C/29 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) Figure 14.6 TRAIOC Register in Pulse Output Mode Rev.2.10 ...
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R8C/28 Group, R8C/29 Group 14.1.3 Event Counter Mode In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.4 Specifications of Event Counter Mode). Figure 14.7 shows the TRAIOC Register in Event Counter Mode. ...
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R8C/28 Group, R8C/29 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO pin ...
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R8C/28 Group, R8C/29 Group 14.1.4 Pulse Width Measurement Mode In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.5 Specifications of Pulse Width Measurement Mode). Figure 14.8 ...
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R8C/28 Group, R8C/29 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/28 Group, R8C/29 Group n = high level: the contents of TRA register, low level: the contents of TRAPRE register FFFFh n 0000h Set program 1 TSTART bit in TRACR register 0 1 Measured pulse (TRAIO pin ...
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R8C/28 Group, R8C/29 Group 14.1.5 Pulse Period Measurement Mode In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.6 Specifications of Pulse Period Measurement Mode). Figure 14.10 ...
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R8C/28 Group, R8C/29 Group Timer RA I/O Control Register Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 — (b7-b6) NOTE: 1. When the same value from the TRAIO ...
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R8C/28 Group, R8C/29 Group Underflow signal of timer RA prescaler Set program 1 TSTART bit in TRACR register 0 Starts counting 1 Measurement pulse (TRAIO pin input) 0 Contents of TRA Contents of read-out (1) buffer 1 ...
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R8C/28 Group, R8C/29 Group 14.1.6 Notes on TImer RA • Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts. • Even if the prescaler and timer RA ...
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R8C/28 Group, R8C/29 Group 14.2 Timer RB Timer 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter (refer to Tables 14.7 to 14.10 the Specifications of Each Mode). ...
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R8C/28 Group, R8C/29 Group Timer RB Control Register Symbol TRBCR Bit Symbol TSTART TCSTF TSTOP — (b7-b3) NOTES: 1. Refer to 14.2.5 Notes on Tim er RB for precautions regarding bits TSTART, ...
Page 173
R8C/28 Group, R8C/29 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Timer RB Mode Register Symbol ...
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R8C/28 Group, R8C/29 Group Timer RB Prescaler Register b7 b0 Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Programmable w ait one-shot generation mode NOTE: 1. When the TSTOP bit in the TRBCR register is set to ...
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R8C/28 Group, R8C/29 Group 14.2.1 Timer Mode In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table 14.7 Specifications of Timer Mode). Registers TRBOCR and TRBSC are not used in timer ...
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R8C/28 Group, R8C/29 Group 14.2.1.1 Timer Write Control during Count Operation Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, ...
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R8C/28 Group, R8C/29 Group When the TWRC bit is set to 0 (write to reload register and counter) Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. Count source Reloads register of Previous value ...
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R8C/28 Group, R8C/29 Group 14.2.2 Programmable Waveform Generation Mode In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer ...
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R8C/28 Group, R8C/29 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode Rev.2.10 Sep ...
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R8C/28 Group, R8C/29 Group 1 TSTART bit in TRBCR register 0 Count source Timer RB prescaler underflow signal Counter of timer bit in TRBIC register 0 1 TOPL bit in TRBIO register 0 1 TRBO pin output ...
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R8C/28 Group, R8C/29 Group 14.2.3 Programmable One-shot Generation Mode In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.9 ...
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R8C/28 Group, R8C/29 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) NOTE: 1. Refer to 14.2.3.1 One-Shot Trigger Selection. Figure 14.20 TRBIOC Register ...
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R8C/28 Group, R8C/29 Group 1 TSTART bit in TRBCR register 0 Set program 1 TOSSTF bit in TRBOCR register 0 INT0 pin input Count source Timer RB prescaler underflow signal Counter of timer bit ...
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R8C/28 Group, R8C/29 Group 14.2.3.1 One-Shot Trigger Selection In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count ...
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R8C/28 Group, R8C/29 Group 14.2.4 Programmable Wait One-Shot Generation Mode In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to ...
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R8C/28 Group, R8C/29 Group Timer RB I/O Control Register Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG — (b7-b4) NOTE: 1. Refer to 14.2.3.1 One-Shot Trigger Selection. Figure 14.22 TRBIOC Register ...
Page 187
R8C/28 Group, R8C/29 Group 1 TSTART bit in TRBCR register 0 1 TOSSTF bit in TRBOCR register 0 INT0 pin input Count source Timer RB prescaler underflow signal Counter of timer bit in TRBIC register 0 1 ...
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R8C/28 Group, R8C/29 Group 14.2.5 Notes on Timer RB • Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. • Even if the prescaler and timer RB ...
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R8C/28 Group, R8C/29 Group 14.2.5.2 Programmable waveform generation mode The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the ...
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R8C/28 Group, R8C/29 Group • Workaround example (b): As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by ...
Page 191
R8C/28 Group, R8C/29 Group 14.2.5.4 Programmable wait one-shot generation mode The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), ...
Page 192
R8C/28 Group, R8C/29 Group 14.3 Timer RC 14.3.1 Overview Timer 16-bit timer with four I/O pins. Timer RC uses either f1 or fOCO40M as its operation clock. Table 14.11 lists the Timer RC Operation Clock. Table 14.11 ...
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R8C/28 Group, R8C/29 Group TRCMR register TRCCR1 register TRCIER register TRCSR register TRCIOR0 register TRCIOR1 register TRC register TRCGRA register TRCGRB register TRCGRC register TRCGRD register TRCCR2 register TRCDF register TRCOER register Figure 14.26 Timer RC Block Diagram Table 14.12 ...
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R8C/28 Group, R8C/29 Group 14.3.2 Registers Associated with Timer RC Table 14.13 lists the Registers Associated with Timer RC. Figures 14.27 to 14.36 show details of the registers associated with timer RC. Table 14.13 Registers Associated with Timer RC Timer ...
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R8C/28 Group, R8C/29 Group (1) Timer RC Mode Register Symbol TRCMR Bit Symbol PWMB PWMC PWMD PWM2 BFC BFD — (b6) TSTART NOTES: 1. For notes on PWM2 mode, refer to 14.3.9.5 ...
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R8C/28 Group, R8C/29 Group Timer RC Control Register Symbol TRCCR1 Bit Symbol TOA TOB TOC TOD TCK0 TCK1 TCK2 CCLR NOTES: 1. Set to these bits w hen the TSTART bit ...
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R8C/28 Group, R8C/29 Group Timer RC Interrupt Enable Register Symbol TRCIER Bit Symbol IMIEA IMIEB IMIEC IMIED — (b6-b4) OVIE Figure 14.29 TRCIER Register Rev.2.10 Sep 26, 2008 Page 178 of 441 ...
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R8C/28 Group, R8C/29 Group Timer RC Status Register Symbol TRCSR Bit Symbol IMFA IMFB IMFC IMFD — (b6-b4) OVF NOTE: 1. The w riting results are as follow s: • This bit ...
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R8C/28 Group, R8C/29 Group (1) Timer RC Counter (b15) (b8 Count a count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRCSR register is set to 1. NOTE: 1. Access the ...
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R8C/28 Group, R8C/29 Group Timer RC Control Register Symbol TRCCR2 Bit Symbol — (b4-b0) CSEL TCEG0 TCEG1 NOTES: 1. For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 ...