MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 171

• Manufacturer Part Number: MC908LJ24CPBER
• Description: IC MCU 24K FLASH 4/8MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.4.2 Data Format
10.4.3 Break Signal
10.4.4 Baud Rate
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
The communication baud rate is controlled by the crystal frequency and
the state of the PTC1 pin (when IRQ is set to V
monitor mode. When PTC1 is high, the divide by ratio is 1024. If the
PTC1 pin is at logic 0 upon entry into monitor mode, the divide by ratio
is 512.
If monitor mode was entered with V
set at 1024, regardless of PTC1. If monitor mode was entered with V
on IRQ, then the internal PLL steps up the external frequency, presumed
to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor
mode entry require that the reset vector is blank.
START
BIT
0
BIT 0
1
2
MISSING STOP BIT
BIT 1
Monitor ROM (MON)
3
Figure 10-3. Monitor Data Format
Figure 10-4. Break Transaction
4
BIT 2
5
6
BIT 3
7
BIT 4
DD
BIT 5
on IRQ, then the divide by ratio is
2-STOP BIT DELAY BEFORE ZERO ECHO
BIT 6
0
1
TST
BIT 7
2
) upon entry into
Functional Description
3
Monitor ROM (MON)
STOP
BIT
4
5
START
NEXT
BIT
Data Sheet
6
7
171
SS