MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 181

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MC908LJ24CPBER

Manufacturer Part Number
MC908LJ24CPBER
Description
IC MCU 24K FLASH 4/8MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPBER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
10.6.1 PRGRNGE
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
PRGRNGE is used to program a range of FLASH locations with data
loaded into the data array.
The start location of the FLASH to be programmed is specified by the
address ADDRH:ADDRL and the number of bytes from this location is
specified by DATASIZE. The maximum number of bytes that can be
programmed in one routine call is 255 bytes (max. DATASIZE is 255).
ADDRH:ADDRL do not need to be at a page boundary, the routine
handles any boundary misalignment during programming. A check to
see that all bytes in the specified range are erased is not performed by
this routine prior programming. Nor does this routine do a verification
after programming, so there is no return confirmation that programming
was successful. User must assure that the range specified is first
erased.
The coding example below is to program 64 bytes of data starting at
FLASH location $EF00, with a bus speed of 4.9152 MHz. The coding
assumes the data block is already loaded in RAM, with the address
pointer, FILE_PTR, pointing to the first byte of the data block.
Routine Name
Routine Description
Calling Address
Stack Used
Data Block Format
Monitor ROM (MON)
Table 10-11. PRGRNGE Routine
PRGRNGE
Program a range of locations
$FC06
14 bytes
Bus speed (BUS_SPD)
Data size (DATASIZE)
Start address high (ADDRH)
Start address (ADDRL)
Data 1 (DATA1)
Data N (DATAN)
:
ROM-Resident Routines
Monitor ROM (MON)
Data Sheet
181

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