MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 237

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MC908LJ24CPBER

Manufacturer Part Number
MC908LJ24CPBER
Description
IC MCU 24K FLASH 4/8MHZ 64-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CPBER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
HC08
No. Of I/o's
40
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CPBER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
12.10.5 RTC Status Register (RTCSR)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Address:
The RTC status register contains eight status flags. When a flag is set
and the corresponding interrupt enable bit is also set, a CPU interrupt
request is generated.
ALMF — Alarm Flag
CHRF — Chronograph Flag
Reset:
Read:
Write:
This clearable, read-only bit is set when the value in the RTC hour and
minute counters matches the value in the alarm hour and alarm
minute registers. When the ALMIE bit in RTCCR1 is set, ALMF
generates a CPU interrupt request. In normal operation, clear the
ALMF bit by reading RTCSR with ALMF set and then reading the
alarm hour register (ALHR). Reset clears ALMF.
This clearable, read-only bit is set on every tick of the chronograph
counter (every counter count). The tick is on every 1/128 seconds
(see
RTCCR1 is set, CHRF generates a CPU interrupt request. In normal
operation, clear the CHRF bit by reading RTCSR with CHRF set and
then reading the chronograph data register (CHRR). Reset clears
CHRF.
1 = RTC hour and minute counters matches the
0 = No matching between hour and minute counters and alarm
1 = A chronograph counter tick has occurred
0 = No chronograph counter tick has occurred
12.5.4 Chronograph
$0044
ALMF
alarm hour and minute registers
hour and minute registers
0
Figure 12-10. RTC Status Register (RTCSR)
Real Time Clock (RTC)
= Unimplemented
CHRF
0
DAYF
0
Functions). When the CHRIE bit in
HRF
0
MINF
0
SECF
0
Real Time Clock (RTC)
TB1F
0
RTC Registers
Data Sheet
TB2F
0
237

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