MC908LJ24CPBER Freescale Semiconductor, MC908LJ24CPBER Datasheet - Page 329

• Manufacturer Part Number: MC908LJ24CPBER
• Description: IC MCU 24K FLASH 4/8MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CPBER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 40
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 40
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.5.6 Multi-Master IIC Data Receive Register (MMDRR)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Address:
If the calling master does not return an acknowledge bit (MMRXAK = 1),
the module will release the SDA line for master to generate a "stop" or
"repeated start" condition. The data in the MMDTR will not be transferred
to the output circuit until the next calling from a master. The transmit
buffer empty flag remains cleared (MMTXBE = 0).
In master mode, the data in MMDTR will be transferred to the output
circuit when:
If the slave does not return an acknowledge bit (MMRXAK = 1), the
master will generate a "stop" or "repeated start" condition. The data in
the MMDTR will not be transferred to the output circuit. The transmit
buffer empty flag remains cleared (MMTXBE = 0).
The sequence of events for slave transmit and master transmit are
illustrated in
When the MMIIC module is enabled, MMEN = 1, data in this read-only
register depends on whether module is in master or slave mode.
Reset:
Read: MMRD7
Write:
Figure 15-7. Multi-Master IIC Data Receive Register (MMDRR)
•
•
the module receives an acknowledge bit (MMRXAK = 0), after
setting master transmit mode (MMRW = 0), and the calling
address has been transmitted; or
the previous data in the output circuit has be transmitted and the
receiving slave returns an acknowledge bit, indicated by a
received acknowledge bit (MMRXAK = 0).
$006F
Bit 7
Multi-Master IIC Interface (MMIIC)
0
Figure
= Unimplemented
MMRD6
6
0
15-8.
MMRD5
5
0
MMRD4
4
0
MMRD3
3
0
Multi-Master IIC Interface (MMIIC)
MMRD2
Multi-Master IIC Registers
2
0
MMRD1
1
0
Data Sheet
MMRD0
Bit 0
0
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