MC908LJ24CFUER Freescale Semiconductor, MC908LJ24CFUER Datasheet - Page 118

IC MCU 24K FLASH 8MHZ SPI 64-QFP

MC908LJ24CFUER

Manufacturer Part Number
MC908LJ24CFUER
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFUER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clock Generator Module (CGM)
8.4.6 Programming the PLL
Data Sheet
118
NOTE:
The following conditions apply when in manual mode:
The following procedure shows how to program the PLL.
The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f
2. Calculate the desired VCO frequency, f
3. Choose a practical PLL reference frequency, f
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
Before entering tracking mode (ACQ = 1), software must wait a
given time, t
Specifications.), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
Software must wait a given time, t
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
where P is the power of two multiplier, and can be 0, 1, 2, or 3
reference clock divider, R. Typically, the reference is 32.768kHz
and R = 1.
Frequency errors to the PLL are corrected at a rate of f
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate.
Clock Generator Module (CGM)
f
VCLKDES
ACQ
(See
=
2
P
8.9 Acquisition/Lock Time
×
f
CGMPCLK
=
AL
2
, after entering tracking mode
MC68HC908LJ24/LK24 — Rev. 2.1
P
BUSDES
×
4
VCLKDES
×
f
BUSDES
.
Freescale Semiconductor
RCLK
.
, and the
RCLK
/R. For

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