MC908LJ24CFUER Freescale Semiconductor, MC908LJ24CFUER Datasheet - Page 239

IC MCU 24K FLASH 8MHZ SPI 64-QFP

MC908LJ24CFUER

Manufacturer Part Number
MC908LJ24CFUER
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFUER

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
NOTE:
NOTE:
TB1F — Timebase 1 Flag
Timebase 1 is not synchronized to the compensated RTC 1-Hz clock.
Hence, time intervals for timebase ticks may not align with the RTC clock
and calendar register updates.
TB2F — Timebase 2 Flag
Timebase 2 is not synchronized to the compensated RTC 1-Hz clock.
Hence, time intervals for timebase ticks may not align with the RTC clock
and calendar register updates.
This clearable, read-only bit is set on every tick of the timebase 1
counter (every 0.5 or 0.125 seconds). When the TB1IE bit in RTCCR1
is set, TB1F generates a CPU interrupt request. In normal operation,
clear the TB1F bit by reading RTCSR with TB1F set and then reading
the chronograph data register (CHRR). Reset clears TB1F.
This clearable, read-only bit is set on every tick of the timebase 2
counter (every 0.25 or 0.0625 seconds). When the TB2IE bit in
RTCCR1 is set, TB2F generates a CPU interrupt request. In normal
operation, clear the TB2F bit by reading RTCSR with TB2F set and
then reading the chronograph register (CHRR). Reset clears TB2F.
1 = A timebase 1 tick has occurred
0 = No timebase 1 tick has occurred
1 = A timebase 2 tick has occurred
0 = No timebase 2 tick has occurred
Real Time Clock (RTC)
Real Time Clock (RTC)
RTC Registers
Data Sheet
239

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