R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet
R5F21324ANSP#U1
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R5F21324ANSP#U1 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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R8C/32A Group 16 Hardware Manual RENESAS MCU R8C FAMILY / R8C/3x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) Address XXXXh Bit b7 b6 Symbol XXX7 XXX6 After Reset 0 0 Bit Symbol b0 XXX0 XXX bit b1 XXX1 b2 — ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. Asynchronous Communication ...
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SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Features ..................................................................................................................................................... 1 1.1.1 Applications .......................................................................................................................................... 1 1.1.2 Specifications ........................................................................................................................................ 2 1.2 Product List ............................................................................................................................................... 4 1.3 Block Diagram ......................................................................................................................................... 5 1.4 Pin Assignment .......................................................................................................................................... 6 1.5 Pin ...
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Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 36 5.8 Reset Source Determination Function ..................................................................................................... 36 6. Voltage Detection Circuit .............................................................................................................. 37 6.1 Overview ................................................................................................................................................. 37 6.2 Registers .................................................................................................................................................. 41 6.2.1 Voltage Monitor Circuit/Comparator A Control Register (CMPA) ................................................... 41 6.2.2 ...
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Bus ................................................................................................................................................ 87 9. Clock Generation Circuit ............................................................................................................... 89 9.1 Overview ................................................................................................................................................. 89 9.2 Registers .................................................................................................................................................. 92 9.2.1 System Clock Control Register 0 (CM0) ............................................................................................ 92 9.2.2 System Clock Control Register 1 (CM1) ............................................................................................ 93 9.2.3 System Clock Control ...
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Protect Register (PRCR) ................................................................................................................... 120 11. Interrupts ..................................................................................................................................... 121 11.1 Overview ............................................................................................................................................... 121 11.1.1 Types of Interrupts ............................................................................................................................ 121 11.1.2 Software Interrupts ........................................................................................................................... 122 11.1.3 Special Interrupts .............................................................................................................................. 123 11.1.4 Peripheral Function Interrupts .......................................................................................................... 123 11.1.5 Interrupts and Interrupt ...
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Forced Erase Function ........................................................................................................................... 150 12.4 Standard Serial II/O Mode Disabled Function ...................................................................................... 150 12.5 Notes on ID Code Areas ........................................................................................................................ 151 12.5.1 Setting Example of ID Code Areas ................................................................................................... 151 13. Option Function Select Area ....................................................................................................... 152 13.1 ...
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DTC Activation Source Acknowledgement and Interrupt Source Flags .......................................... 183 15.4 Notes on DTC ........................................................................................................................................ 185 15.4.1 DTC activation source ...................................................................................................................... 185 15.4.2 DTCENi ( Registers .................................................................................................. 185 15.4.3 Peripheral Modules ........................................................................................................................... 185 ...
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Programmable One-shot Generation Mode ........................................................................................... 216 18.5.1 Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode ............ 217 18.5.2 Operating Example ........................................................................................................................... 218 18.5.3 One-Shot Trigger Selection .............................................................................................................. 219 18.6 Programmable Wait One-Shot Generation Mode ................................................................................. 220 ...
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Timer RC Control Register 1 (TRCCR1) in PWM Mode ................................................................ 259 19.6.2 Timer RC Control Register 2 (TRCCR2) in PWM Mode ................................................................ 259 19.6.3 Operating Example ........................................................................................................................... 261 19.7 PWM2 Mode ......................................................................................................................................... 263 19.7.1 Timer RC Control Register 1 ...
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UART0 Receive Buffer Register (U0RB) ........................................................................................ 297 21.2.7 UART0 Pin Select Register (U0SR) ................................................................................................. 298 21.3 Clock Synchronous Serial I/O Mode ..................................................................................................... 299 21.3.1 Measure for Dealing with Communication Errors ........................................................................... 303 21.3.2 Polarity Select Function .................................................................................................................... 304 21.3.3 ...
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SDA Input ......................................................................................................................................... 349 22.5.6 ACK and NACK ............................................................................................................................... 349 22.5.7 Initialization of Transmission/Reception .......................................................................................... 349 22.6 Multiprocessor Communication Function ............................................................................................. 350 22.6.1 Multiprocessor Transmission ............................................................................................................ 353 22.6.2 Multiprocessor Reception ................................................................................................................. 354 22.6.3 RXD2 Digital Filter Select Function ................................................................................................ ...
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SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 393 25.2.3 I/O Function Pin Select Register (PINSR) ....................................................................................... 394 25.2.4 IIC bus Transmit Data Register (ICDRT) ......................................................................................... 395 25.2.5 IIC bus Receive Data Register (ICDRR) .......................................................................................... 395 25.2.6 IIC bus Control Register ...
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A/D Register i (ADi ...................................................................................................... 445 27.2.3 A/D Mode Register (ADMOD) ........................................................................................................ 446 27.2.4 A/D Input Select Register (ADINSEL) ............................................................................................ 447 27.2.5 A/D Control Register 0 (ADCON0) ................................................................................................. 448 27.2.6 A/D Control Register 1 ...
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Flash Memory ............................................................................................................................. 487 30.1 Overview ............................................................................................................................................... 487 30.2 Memory Map ......................................................................................................................................... 488 30.3 Functions to Prevent Flash Memory from being Rewritten .................................................................. 489 30.3.1 ID Code Check Function .................................................................................................................. 489 30.3.2 ROM Code Protect Function ............................................................................................................ 490 30.3.3 ...
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Oscillation Stop Detection Function ................................................................................................. 555 33.1.4 Oscillation Circuit Constants ............................................................................................................ 555 33.2 Notes on Interrupts ................................................................................................................................ 556 33.2.1 Reading Address 00000h .................................................................................................................. 556 33.2.2 SP Setting .......................................................................................................................................... 556 33.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 556 33.2.4 ...
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Countermeasures against Noise Error of Port Control Registers ..................................................... 577 34. Notes on On-Chip Debugger ...................................................................................................... 578 Appendix 1. Package Dimensions ........................................................................................................ 579 Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 580 Appendix 3. Example ...
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SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Module Standby Control Register 0009h System Clock Control ...
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Address Register 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC Activation Enable Register 3 008Ch 008Dh ...
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Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register ...
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Address Register 0180h Timer RA Pin Select Register 0181h Timer RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h 0185h 0186h 0187h 0188h UART0 Pin Select Register 0189h 018Ah UART2 ...
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Address Register 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC Transfer Vector Area 2C07h DTC Transfer ...
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Address Register 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTC ...
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R8C/32A Group RENESAS MCU 1. Overview 1.1 Features The R8C/32A Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/32A Group. Table 1.1 Specifications for R8C/32A Group (1) Item Function CPU Central processing ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 1.2 Specifications for R8C/32A Group (2) Item Function Serial UART0 Interface UART2 Synchronous Serial Communication Unit (SSU bus LIN Module ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1.2 Product List Table 1.3 lists Product List for R8C/32A Group, and Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/32A ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1.3 Block Diagram Figure 1.2 shows a Block Diagram. I/O ports Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1.4 Pin Assignment Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number. P4_2/VREF P4_7/XOUT(/XCOUT) P4_6/XIN(/XCIN) VCC/AVCC ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 1.4 Pin Name Information by Pin Number Pin Control Pin Port Number 1 P4_2 2 MODE 3 RESET 4 XOUT(/XCOUT) P4_7 5 VSS/AVSS ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 1.5 Pin Functions Tables 1.5 and 1.6 list Pin Functions. Table 1.5 Pin Functions (1) Item Pin Name Power supply input VCC, VSS Analog ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 1.6 Pin Functions (2) Item Reference voltage input VREF A/D converter AN8 to AN11 ADTRG Comparator A LVCMP1, LVCMP2 LVREF LVCOUT1, LVCOUT2 Comparator ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 3. Memory 3.1 R8C/32A Group Figure 3 Memory Map of R8C/32A Group. The R8C/32A Group has a 1-Mbyte address space from addresses ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.12 list the ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.2 SFR Information (2) Address 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.3 SFR Information (3) Address 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.6 SFR Information (6) Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.7 SFR Information (7) Address 0180h Timer RA Pin Select Register 0181h Timer RC Pin Select Register 0182h Timer RC Pin Select Register ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.8 SFR Information (8) Address 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.9 SFR Information (9) Address 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.10 SFR Information (10) Address 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.11 SFR Information (11) Address 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 4.12 SFR Information (12) Address 2CF0h DTC Control Data 22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTC Control Data 23 2CF9h ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.1 Registers 5.1.1 Processor Mode Register 0 (PM0) Address 0004h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.1.3 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS When shipping 1 Bit Symbol b0 WDTON Watchdog timer start select ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.1.4 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — When shipping 1 Bit Symbol b0 WDTUFS0 Watchdog timer underflow period ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.2 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group VCC RESET Figure 5.4 Example of Hardware Reset Circuit and Operation RESET Figure 5.5 Example of Hardware Reset Circuit (Usage Example of External Supply ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.3 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.4 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.5 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 5.7 Cold Start-Up/Warm Start-Up Determination Function The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6. Voltage Detection Circuit The voltage detection circuit monitors the voltage input to the VCC pin. This circuit can be used to monitor the ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group LVCMP2 VCC Level Selection Circuit (16 levels) VD1S3 to VD1S0 Level Selection Circuit (4 levels) VDSEL1 to VDSEL0 Figure 6.1 Voltage Detection Circuit Block ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Voltage detection 0 circuit Level selection VCC VDSEL1 to VDSEL0 Internal reference voltage VW0C0: Bit in VW0C register VCA25: Bit in VCA2 register VDSEL0, ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Voltage detection 2 circuit fOCO-S VCA27 VCA24 = 1 LVCMP2 VCC + VCA24 = 0 Voltage - detection 2 VCA23 = 0 signal Internal ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2 Registers 6.2.1 Voltage Monitor Circuit/Comparator A Control Register (CMPA) Address 0030h Bit b7 b6 Symbol COMPSEL After Reset 0 Bit Symbol b0 CM1POR ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) Address 0031h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2.4 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset The LVDAS bit in the OFS register is ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2.5 Voltage Detection 1 Level Select Register (VD1LS) Address 0036h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 VD1S0 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) Address 0038h Bit b7 b6 Symbol — — After Reset The LVDAS bit in the OFS ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C) Address 0039h Bit b7 b6 Symbol VW1C7 — After Reset 1 0 Bit Symbol b0 VW1C0 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C) Address 003Ah Bit b7 b6 Symbol VW2C7 — After Reset 1 0 Bit Symbol b0 VW2C0 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.2.9 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS When shipping 1 Bit Symbol b0 WDTON Watchdog timer start select ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.3 VCC Input Voltage 6.3.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.3.2 Monitoring Vdet1 Once the following settings are made, the comparison result of ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.4 Voltage Monitor 0 Reset To use voltage monitor 0 reset, set the LVDAS bit in the OFS register to 0 (voltage monitor 0 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.5 Voltage Monitor 1 Interrupt Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an Operating ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Vdet1 (1) 1.8 V VW1C3 bit VW1C2 bit VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 6.6 Voltage Monitor 2 Interrupt Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an Operating ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group VCC or LVCMP2 Vdet2 (1) 1.8 V VCA13 bit VW2C2 bit VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7. I/O Ports There are 15 I/O ports P1, P3_3 to P3_5, P3_7, and P4_5 to P4_7 (P4_6 and P4_7 can be used as ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.2 Effect on Peripheral Functions I/O ports function as I/O ports for peripheral functions (Refer to Table 1.4 Pin Name Information by Pin Number). ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group P1_0 to P1_2 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group P1_4 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function P1_5 Direction register ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group P1_6 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group P3_3 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group P3_5 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function P3_7 Direction register ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group P4_2/VREF Data bus P4_5 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group P4_6/XIN/XCIN Pull-up selection Direction register Data bus Port latch IOINSEL P4_7/XOUT/XCOUT Pull-up selection Direction register Data bus Port latch IOINSEL Note: 1. symbolizes a ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group MODE MODE signal input RESET RESET signal input Note: 1. Ensure the input voltage to each port does not exceed VCC. Figure 7.8 Configuration ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4 Registers 7.4.1 Port Pi Direction Register (PDi Address 00E3h (PD1), 00E7h (PD3 Bit b7 b6 Symbol PDi_7 PDi_6 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.2 Port Pi Register (Pi Address 00E1h(P1), 00E5h(P3 Bit b7 b6 Symbol Pi_7 Pi_6 After Reset X X Bit ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.3 Timer RA Pin Select Register (TRASR) Address 0180h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TRAIOSEL0 TRAIO ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) Address 0182h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TRCIOASEL0 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.7 UART0 Pin Select Register (U0SR) Address 0188h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD0SEL0 TXD0 pin ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.8 UART2 Pin Select Register 0 (U2SR0) Address 018Ah Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD2SEL0 TXD2/SDA2 ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.10 SSU/IIC Pin Select Register (SSUIICSR) Address 018Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 IICSEL 2 SSU/I ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.12 I/O Function Pin Select Register (PINSR) Address 018Fh Bit b7 b6 Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL After Reset 0 0 Bit Symbol ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.13 Pull-Up Control Register 0 (PUR0) Address 01E0h Bit b7 b6 Symbol PU07 PU06 After Reset 0 0 Bit Symbol b0 — Reserved bits ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.15 Port P1 Drive Capacity Control Register (P1DRR) Address 01F0h Bit b7 b6 Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0 After Reset ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.16 Drive Capacity Control Register 0 (DRR0) Address 01F2h Bit b7 b6 Symbol DRR07 DRR06 After Reset 0 0 Bit Symbol b0 — Reserved ...
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Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.4.18 Input Threshold Control Register 0 (VLT0) Address 01F5h Bit b7 b6 Symbol VLT07 VLT06 After Reset 0 0 Bit Symbol b0 — Reserved ...
Page 107
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.5 Port Settings Tables 7.5 to 7.25 list the port settings. Table 7.5 Port P1_0/KI0/AN8/TRCIOD/LVCMP1 Register PD1 KIEN CH Bit PD1_0 KI0EN 2 1 ...
Page 108
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.7 Port P1_2/KI2/AN10/TRCIOB/LVREF Register PD1 KIEN ADINSEL CH Bit PD1_2 KI2EN ...
Page 109
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.9 Port P1_4/TXD0/TRCCLK Register PD1 U0SR Bit PD1_4 TXD0SEL0 Setting Value ...
Page 110
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.12 Port P1_7/INT1/TRAIO/IVCMP1 Register PD1 TRASR TRAIOSEL Bit PD1_7 Other than 01b 1 Other than 01b Setting ...
Page 111
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.14 Port P3_4/TRCIOC/SSI/RXD2/SCL2/TXD2/SDA2/IVREF3 Synchronous Serial Communication Unit (Refer to Table 24.4 Register PD3 SSUIICSR Association between Communication Modes and I/O Pins .) SSI ...
Page 112
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.15 Port P3_5/SCL/SSCK/TRCIOD/CLK2 Register PD3 SSUIICSR ICCR1 Bit PD3_5 IICSEL ICE ...
Page 113
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.17 Port P4_2/VREF Register ADCON1 Bit ADSTBY 0 Setting Value 1 Table 7.18 Port P4_5/INT0/RXD2/SCL2/ADTRG Register PD4 INTEN Bit PD4_5 INT0EN 0 X ...
Page 114
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.20 Port P4_7/XOUT/XCOUT Register PD4 CM0 Bit PD4_7 CM01 CM03 CM04 CM05 CM10 CM11 CM12 CM13 ...
Page 115
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 7.21 TRBO Pin Setting Register TRBIOC Bit (1) TOCNT 0 0 Setting value 0 1 Note: 1. Set the TOCNT bit in the ...
Page 116
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 7.6 Unassigned Pin Handling Table 7.26 lists Unassigned Pin Handling. Figure 7.9 shows the Unassigned Pin Handling. Table 7.26 Unassigned Pin Handling Pin Name ...
Page 117
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 8. Bus The bus cycles differ when accessing ROM/RAM and when accessing SFR. Table 8.1 lists Bus Cycles by Access Area of R8C/32A Group ...
Page 118
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and ...
Page 119
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9. Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit: • XIN clock oscillation circuit • XCIN clock oscillation ...
Page 120
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group S Q CM10 = 1 (stop mode) R RESET Power-on reset Software reset Interrupt request S Q WAIT instruction R CM30 Stop signal XOUT/XCOUT ...
Page 121
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group fC fC4 fC32 fOCO40M fOCO128 fOCO fOCO-F fOCO-WDT INT0 Timer f32 CPU clock Figure 9.2 Peripheral Function Clock REJ09B0458-0020 ...
Page 122
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2 Registers 9.2.1 System Clock Control Register 0 (CM0) Address 0006h Bit b7 b6 Symbol CM07 CM06 After Reset 0 0 Bit Symbol Bit ...
Page 123
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2.2 System Clock Control Register 1 (CM1) Address 0007h Bit b7 b6 Symbol CM17 CM16 After Reset 0 0 Bit Symbol b0 CM10 All ...
Page 124
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2.3 System Clock Control Register 3 (CM3) Address 0009h Bit b7 b6 Symbol CM37 CM36 After Reset 0 0 Bit Symbol b0 CM30 Wait ...
Page 125
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2.4 Oscillation Stop Detection Register (OCD) Address 000Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 OCD0 Oscillation stop ...
Page 126
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0) Address 0023h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA00 ...
Page 127
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2) Address 0025h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA20 ...
Page 128
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2.10 High-Speed On-Chip Oscillator Control Register 4 (FRA4) Address 0029h Bit b7 b6 Symbol — — After Reset When shipping Bit b7-b0 36.864 MHz ...
Page 129
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.2.14 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset The LVDAS bit in the OFS register is ...
Page 130
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Procedure for enabling reduced internal power consumption using VCA20 bit Enter low-speed clock mode or Step (1) low-speed on-chip oscillator mode Stop XIN clock ...
Page 131
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group The clocks generated by the clock generation circuits are described below. 9.3 XIN Clock The XIN clock is supplied by the XIN clock oscillation ...
Page 132
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.4 On-Chip Oscillator Clock The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed on- chip oscillator). This clock ...
Page 133
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.5 XCIN Clock The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the ...
Page 134
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.6 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the ...
Page 135
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.6.7 fOCO-S fOCO operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by ...
Page 136
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.7 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating ...
Page 137
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.7.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division used as the CPU clock. If ...
Page 138
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.7.2 Wait Mode Since the CPU clock stops in wait mode, the CPU operating with the CPU clock and the watchdog timer when count ...
Page 139
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.7.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by the ...
Page 140
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Figure 9.6 shows the Time from Wait Mode to Interrupt Routine Execution after CM30 Bit in CM3 Register is Set to 1 (MCU Enters ...
Page 141
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed. To use a peripheral function interrupt to ...
Page 142
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.7.3 Stop Mode Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral function clocks stop and the CPU and ...
Page 143
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.7.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 9.8 shows the Time from Stop Mode ...
Page 144
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Figure 9.9 shows the State Transitions in Power Control Mode. State Transitions in Power Control Mode Standard operating mode CM14 = 0 OCD2 = ...
Page 145
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.8 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function ...
Page 146
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.8.1 How to Use Oscillation Stop Detection Function • The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the ...
Page 147
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Table 9.6 Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Generated Interrupt Source Oscillation ...
Page 148
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Determination of Interrupt sources NO OCD3 = 1? (XIN clock stops) YES (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock ...
Page 149
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 9.9 Notes on Clock Generation Circuit 9.9.1 Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU ...
Page 150
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 10. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the ...
Page 151
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11. Interrupts 11.1 Overview 11.1.1 Types of Interrupts Figure 11.1 shows the Types of Interrupts. Software (non-maskable interrupts) Interrupts Hardware Notes: 1. Peripheral function ...
Page 152
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 11.1.2.1 Undefined Instruction Interrupt An undefined instruction ...
Page 153
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.1.3 Special Interrupts Special interrupts are non-maskable. 11.1.3.1 Watchdog Timer Interrupt A watchdog timer interrupt is generated by the watchdog timer. For details, refer ...
Page 154
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. ...
Page 155
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 11.2 lists ...
Page 156
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.2 Registers 11.2.1 Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch ...
Page 157
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.2.2 Interrupt Control Register (FMRDYIC, TRCIC, SSUIC/IICIC) Address 0041h (FMRDYIC), 0047h (TRCIC), 004Fh (SSUIC/IICIC Bit b7 b6 Symbol — — After Reset X X ...
Page 158
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.2.3 INTi Interrupt Control Register (INTiIC Address 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) Bit b7 b6 Symbol — — ...
Page 159
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.3 Interrupt Control The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. ...
Page 160
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.3.4 Interrupt Sequence The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is ...
Page 161
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.3.5 Interrupt Response Time Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is ...
Page 162
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.3.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order ...
Page 163
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure ...
Page 164
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.3.8 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which ...
Page 165
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.3.10 Interrupt Priority Level Selection Circuit The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 11.8 shows the ...
Page 166
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.4 INT Interrupt 11.4.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. To use the INTi ...
Page 167
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.4.3 External Input Enable Register 0 (INTEN) Address 01FAh Bit b7 b6 Symbol INT3PL INT3EN After Reset 0 0 Bit Symbol b0 INT0EN INT0 ...
Page 168
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.4.5 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 ...
Page 169
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.5 Key Input Interrupt A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key ...
Page 170
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.5.1 Key Input Enable Register 0 (KIEN) Address 01FEh Bit b7 b6 Symbol KI3PL KI3EN After Reset 0 0 Bit Symbol b0 KI0EN KI0 ...
Page 171
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.6 Address Match Interrupt An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi ...
Page 172
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.6.1 Address Match Interrupt Enable Register i (AIERi Address 01C3h (AIER0), 01C7h (AIER1) Bit b7 b6 Symbol — — ...
Page 173
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.7 Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) The ...
Page 174
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group As with other maskable interrupts, the timer RC interrupt, synchronous serial communication unit interrupt, I bus interface interrupt, and flash memory interrupt are controlled ...
Page 175
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.8 Notes on Interrupts 11.8.1 Reading Address 00000h Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the ...
Page 176
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.8.4 Changing Interrupt Sources The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. ...
Page 177
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 11.8.5 Rewriting Interrupt Control Register (a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that ...
Page 178
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12. ID Code Areas The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard ...
Page 179
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12.2 Functions The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector ...
Page 180
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12.3 Forced Erase Function This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the ...
Page 181
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 12.5 Notes on ID Code Areas 12.5.1 Setting Example of ID Code Areas As the ID code areas are allocated in the flash memory ...
Page 182
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13. Option Function Select Area 13.1 Overview The option function select area is used to select the MCU state after a reset, the function ...
Page 183
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13.2 Registers Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O ...
Page 184
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13.2.2 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — When shipping 1 Bit Symbol b0 WDTUFS0 Watchdog timer underflow period ...
Page 185
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 13.3 Notes on Option Function Select Area 13.3.1 Setting Example of Option Function Select Area As the option function select area is allocated in ...
Page 186
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14. Watchdog Timer The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is ...
Page 187
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group Prescaler 1/16 1/128 CPU clock 1/2 Low-speed on-chip oscillator for watchdog timer Oscillation starts when CSPRO = 1 Internal reset signal (Low active) Bits ...
Page 188
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14.2 Registers 14.2.1 Processor Mode Register 1 (PM1) Address 0005h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — ...
Page 189
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14.2.4 Watchdog Timer Control Register (WDTC) Address 000Fh Bit b7 b6 Symbol WDTC7 — After Reset 0 0 Bit Symbol b0 — The following ...
Page 190
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14.2.6 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS When shipping 1 Bit Symbol b0 WDTON Watchdog timer start select ...
Page 191
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14.2.7 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — When shipping 1 Bit Symbol b0 WDTUFS0 Watchdog timer underflow period ...
Page 192
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14.3 Functional Description 14.3.1 Common Items for Multiple Modes 14.3.1.1 Refresh Acknowledgment Period The period for acknowledging refreshment operation to the watchdog timer (write ...
Page 193
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14.3.2 Count Source Protection Mode Disabled The count source for the watchdog timer is the CPU clock when count source protection mode is disabled. ...
Page 194
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 14.3.3 Count Source Protection Mode Enabled The count source for the watchdog timer is the low-speed on-chip oscillator clock for the watchdog timer when ...
Page 195
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15. DTC The DTC (data transfer controller function that transfers data between the SFR and on-chip memory without using the CPU. This ...
Page 196
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group DTCENi ( DTCTL Peripheral interrupt request Interrupt controller Figure 15.1 DTC Block Diagram 15.2 Registers When the DTC ...
Page 197
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15.2.1 DTC Control Register j (DTCCRj 23) Address See Table 15.4 Control Data Allocation Addresses. Bit b7 b6 Symbol — ...
Page 198
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15.2.3 DTC Transfer Count Register j (DTCCTj 23) Address See Table 15.4 Control Data Allocation Addresses. Bit b7 b6 Symbol ...
Page 199
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15.2.7 DTC Activation Enable Register i (DTCENi Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Dh ...
Page 200
Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/32A Group 15.2.8 DTC Activation Control Register (DTCTL) Address 0080h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Reserved bit ...