R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 380

• Manufacturer Part Number: R5F21334CNFP#U0
• Description: MCU 1KB FLASH 16K ROM 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/33Cr

Specifications of R5F21334CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 350 of 589
Figure 22.10
Figure 22.11
22.4.4
22.4.5
The data written to the U2TB register has its logic inverted before being transmitted. Similarly, the received
data has its logic inverted when read from the U2RB register. Figure 22.10 shows the Serial Data Logic
Switching.
This function inverts the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all I/O data
(including bits for start, stop, and parity) are inverted. Figure 22.11 shows the TXD and RXD I/O Inversion.
(1) U2LCH bit in U2C1 Register = 0 (not inverted)
(2) U2LCH Bit in U2C1 Register = 1 (inverted)
The above applies when:
Transfer clock
TXD2
(not inverted)
Transfer clock
TXD2
(inverted)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock)
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
Serial Data Logic Switching Function
TXD and RXD I/O Polarity Inverse Function
(1) IOPOL Bit in U2MR Register = 0 (not inverted)
(2) IOPOL Bit in U2MR Register = 1 (inverted)
The above applies when:
Serial Data Logic Switching
Transfer clock
TXD2
(not inverted)
RXD2
(not inverted)
Transfer clock
TXD2
(inverted)
RXD2
(inverted)
TXD and RXD I/O Inversion
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
ST
ST
D0
D0
ST
ST
ST
ST
D1
D1
D0
D0
D0
D0
D2
D2
D1
D1
D1
D1
D3
D3
D2
D2
D2
D2
D4
D4
D3
D3
D3
D3
D5
D5
D4
D4
D4
D4
D6
D6
D5
D5
D5
D5
ST: Start bit
P: Parity bit
SP: Stop bit
D7
D7
D6
D6
D6
D6
D7
D7
D7
D7
P
P
SP
SP
P
P
P
P
22. Serial Interface (UART2)
ST: Start bit
P: Parity bit
SP: Stop bit
SP
SP
SP
SP