R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 392

• Manufacturer Part Number: R5F21334CNFP#U0
• Description: MCU 1KB FLASH 16K ROM 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/33Cr

Specifications of R5F21334CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 362 of 589
22.6
Figure 22.17
When the multiprocessor communication function is used, data transmission/reception can be performed between a
number of processors sharing communication lines by asynchronous serial communication, in which a
multiprocessor bit is added to the data. For multiprocessor communication, each receiving station is addressed by a
unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle for
specifying the receiving station, and a data transmission cycle for the specified receiving station. The
multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. When
the multiprocessor bit is set to 1, the cycle is an ID transmission cycle; when the multiprocessor bit is set to 0, the
cycle is a data transmission cycle. Figure 22.17 shows an Inter-Processor Communication Example Using
Multiprocessor Format (Data AAh Transmission to Receiving Station A).
The transmitting station first sends the ID code of the receiving station to perform communication as
communication data with a 1 multiprocessor bit added. It then sends transmit data as communication data with a 0
multiprocessor bit added.
When communication data in which the multiprocessor bit is 1 is received, the receiving station compares that data
with its own ID. If they match, the data to be sent next is received. If they do not match, the receive station
continues to skip communication data until data in which the multiprocessor bit is 1 is again received.
UART2 uses the MPIE bit in the U2SMR5 register to implement this function. When the MPIE bit is set to 1, data
transfer from the UART2 receive register to the U2RB register, receive error detection, and the settings of the status
flags, the RI bit in the U2C1 register, bits FER and OER in the U2RB register, are disabled until data in which the
multiprocessor bit is 1 is received. On receiving a receive character in which the multiprocessor bit is 1, the MPRB
bit in the U2RB register is set to 1 and the MPIE in the U2SMR5 register bit is set to 0, thus normal reception is
resumed.
When the multiprocessor format is specified, the parity bit specification is invalid. All other bit settings are the
same as those in normal asynchronous mode (UART mode). The clock used for multiprocessor communication is
the same as that in normal asynchronous mode (UART mode).
Figure 22.18 shows a Block Diagram of Multiprocessor Communication Function.
Table 22.14 lists the Registers and Settings in Multiprocessor Communication Function.
Multiprocessor Communication Function
Serial data
(Data AAh Transmission to Receiving Station A)
Inter-Processor Communication Example Using Multiprocessor Format
Transmitting
Receiving
station A
(ID = 01)
station
MPRB: Multiprocessor bit
ID transmission cycle
= receiving station
specification
Receiving
(MPRB = 1)
station B
01h
(ID = 02)
Communication line
Data transmission cycle
= data transmission to
receiving station
specified by ID
Receiving
station C
(ID = 03)
(MPRB = 0)
AAh
Receiving
station D
(ID = 04)
22. Serial Interface (UART2)