R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 431

MCU 1KB FLASH 16K ROM 32-LQFP

R5F21334CNFP#U0

Manufacturer Part Number
R5F21334CNFP#U0
Description
MCU 1KB FLASH 16K ROM 32-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/33Cr
Datasheet

Specifications of R5F21334CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
27
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 401 of 589
Figure 24.13
24.5.4
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as
the master device) and check the arbitration of the SCS pin before starting serial transfer. If synchronous serial
communication unit detects that the synchronized internal SCS signal is held “L” in this period, the CE bit in
the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 24.13 shows the Arbitration Check Timing.
Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error)
before starting transmission.
(synchronization)
SSCRH register
Transfer start
Internal SCS
SCS Pin Control and Arbitration
SCS output
MSS bit in
SCS input
Arbitration Check Timing
CE
High-impedance
During arbitration detection
Data write to
SSTDR register
24. Synchronous Serial Communication Unit (SSU)
Maximum time of SCS internal
synchronization

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