R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 469

• Manufacturer Part Number: R5F21334CNFP#U0
• Description: MCU 1KB FLASH 16K ROM 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/33Cr

Specifications of R5F21334CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 439 of 589
25.8
Figure 25.21
Table 25.7
1Tcyc = 1/f1(s)
When the I
•
•
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 25.21 shows the Bit Synchronization Circuit Timing and Table 25.7 lists the Time between Changing SCL
Signal from “L” Output to High-Impedance and Monitoring SCL Signal.
The SCL signal is driven L level by a slave device
The rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Bit Synchronization Circuit
CKS3
2
C bus interface is set to master mode, the high-level period may become shorter if:
0
1
Bit Synchronization Circuit Timing
Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring SCL Signal
ICCR1 Register
SCL monitor timing
Reference clock of
Internal SCL
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
SCL Monitoring Time
25. I
2
C bus Interface