R5F21334CNFP#U0 Renesas Electronics America, R5F21334CNFP#U0 Datasheet - Page 486

• Manufacturer Part Number: R5F21334CNFP#U0
• Description: MCU 1KB FLASH 16K ROM 32-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/33Cr

Specifications of R5F21334CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 27
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/33C Group
REJ09B0570-0100 Rev.1.00 Dec. 14, 2009
Page 456 of 589
27. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3.
27.1
Table 27.1
Notes:
A/D conversion method
Analog input voltage
Operating clock φ AD
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
( φ AD = fAD)
Table 27.1 lists the A/D Converter Performance. Figure 27.1 shows a Block Diagram of A/D Converter.
1. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
2. Refer to Table 32.3 A/D Converter Characteristics for the operating clock φ A/D.
3. The conversion rate per pin is minimum 43 φ AD cycles for 8-bit and 10-bit resolution.
in 10-bit mode and FFh in 8-bit mode.
Overview
(3)
Item
A/D Converter Performance
(1)
(2)
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
fAD, fAD divided by 2, fAD divided by 4, fAD divided by 8
(fAD=f1 or fOCO-F)
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φ AD = 20 MHz
AVCC = Vref = 3.3 V, φ AD = 16 MHz
AVCC = Vref = 3.0 V, φ AD = 10 MHz
AVCC = Vref = 2.2 V, φ AD = 5 MHz
One-shot mode, repeat mode 0, repeat mode 1, single sweep mode,
and repeat sweep mode
12 pins (AN0 to AN11)
• Software trigger
• Timer RC
• External trigger
Minimum 43 φ AD cycles
(Refer to 27.3.3 A/D Conversion Start Condition .)
• 8-bit resolution
• 10-bit resolution ±3 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
• 8-bit resolution
• 10-bit resolution ±5 LSB
±2 LSB
±2 LSB
±2 LSB
±2 LSB
Performance
27. A/D Converter