MC908LJ24CFQE Freescale Semiconductor, MC908LJ24CFQE Datasheet - Page 141

• Manufacturer Part Number: MC908LJ24CFQE
• Description: IC MCU 24K FLASH 8MHZ SPI 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ24CFQE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 48
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Controller Family/series: HC08
• No. Of I/o's: 48
• Ram Memory Size: 768Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 4
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
PIN LOGIC
RESET
Signal Name
CGMXCLK
CGMPCLK
CGMOUT
PORRST
ICLK
IRST
R/W
IAB
IDB
V
DD
INTERNAL
PULLUP
DEVICE
Internal RC oscillator clock
Buffered version of OSC1 from the oscillator module
The divided PLL output
PLL-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
SIM RESET STATUS REGISTER
RESET PIN CONTROL
Table 9-1. Signal Name Conventions
POR CONTROL
AND PRIORITY DECODE
STOP/WAIT
INTERRUPT CONTROL
CONTROL
CONTROL
Figure 9-1. SIM Block Diagram
CLOCK
System Integration Module (SIM)
CLOCK GENERATORS
RESET
COUNTER
SIM
÷ 2
CONTROL
MASTER
RESET
Description
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
COP CLOCK
ICLK (FROM OSC)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS
(FROM ADDRESS MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
System Integration Module (SIM)
Introduction
Data Sheet
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