MC908LJ24CFQE Freescale Semiconductor, MC908LJ24CFQE Datasheet - Page 295

IC MCU 24K FLASH 8MHZ SPI 80-QFP

MC908LJ24CFQE

Manufacturer Part Number
MC908LJ24CFQE
Description
IC MCU 24K FLASH 8MHZ SPI 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFQE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
48
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Controller Family/series
HC08
No. Of I/o's
48
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CFQE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
CAPTURE STROBE
FOR REFERENCE
SPSCK; CPOL = 0
MASTER SS
SPSCK; CPOL =1
SPSCK CYCLE #
MISO/MOSI
FROM MASTER
SS; TO SLAVE
SLAVE SS
SLAVE SS
CPHA = 0
CPHA = 1
FROM SLAVE
MOSI
MISO
Figure 14-4. Transmission Format (CPHA = 0)
When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.
Serial Peripheral Interface Module (SPI)
MSB
Figure 14-5. CPHA/SS Timing
BYTE 1
MSB
1
BIT 6
BIT 6
2
BIT 5
BIT 5
3
BYTE 2
BIT 4
BIT 4
4
BIT 3
BIT 3
5
Serial Peripheral Interface Module (SPI)
BIT 2
BIT 2
6
BYTE 3
BIT 1
BIT 1
7
LSB
LSB
8
Transmission Formats
Data Sheet
295

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