MC908LJ24CFQE Freescale Semiconductor, MC908LJ24CFQE Datasheet - Page 99

IC MCU 24K FLASH 8MHZ SPI 80-QFP

MC908LJ24CFQE

Manufacturer Part Number
MC908LJ24CFQE
Description
IC MCU 24K FLASH 8MHZ SPI 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908LJ24CFQE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
48
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Controller Family/series
HC08
No. Of I/o's
48
Ram Memory Size
768Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08LJ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908LJ24CFQE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP
NOP
NSA
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
PSHA
PSHH
PSHX
PULA
PULH
PULX
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP
RSP
Source
Form
Move
Unsigned multiply
Negate (Two’s Complement)
No Operation
Nibble Swap A
Inclusive OR A and M
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Rotate Left through Carry
Rotate Right through Carry
Reset Stack Pointer
Operation
Table 6-1. Instruction Set Summary (Sheet 6 of 8)
Central Processor Unit (CPU)
H:X ← (H:X) + 1 (IX+D, DIX+)
(M)
Push (H); SP ← (SP) – 1
Push (A); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
C
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
b7
A ← (A[3:0]:A[7:4])
Destination
X:A ← (X) × (A)
A ← (A) | (M)
b7
Description
SP ← $FF
None
← (M)
b0
Source
b0
C
V H I N Z C
0 – –
– 0 – – – 0 INH
– – – – – – INH
– – – – – – INH
0 – –
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – – – – – INH
– –
– –
– –
Effect on
CCR
Central Processor Unit (CPU)
DD
DIX+
IMD
IX+D
DIR
INH
INH
IX1
IX
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
9EEA
9EDA
9E60
9E69
9E66
CA
9D
AA
BA
DA
EA
9C
4E
5E
6E
7E
42
30
40
50
60
70
62
FA
87
8B
89
86
8A
88
39
49
59
69
79
36
46
56
66
76
Opcode Map
Data Sheet
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
ff
ff
dd
ff
ff
99
5
4
4
4
5
4
1
1
4
3
5
1
3
2
3
4
4
3
2
4
5
2
2
2
2
2
2
4
1
1
4
3
5
4
1
1
4
3
5
1

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