MC68HC908GP16CFB Freescale Semiconductor, MC68HC908GP16CFB Datasheet

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MC68HC908GP16CFB

Manufacturer Part Number
MC68HC908GP16CFB
Description
MCU 8-BIT 16K FLASH 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC68HC908GP16CFB

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908GP16CFB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
MC68HC908EY16
MC68HC908EY8
Data Sheet
M68HC08
Microcontrollers
MC68HC908EY16
Rev. 10
10/2005
freescale.com

Related parts for MC68HC908GP16CFB

MC68HC908GP16CFB Summary of contents

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MC68HC908EY16 MC68HC908EY8 Data Sheet M68HC08 Microcontrollers MC68HC908EY16 Rev. 10 10/2005 freescale.com ...

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...

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... For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...

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... MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

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... Timer Interface A (TIMA) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Chapter 18 Timer Interface B (TIMB) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Chapter 19 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 Chapter 20 Electrical Specifications 241 Chapter 21 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . 253 Appendix A MC68HC908EY8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 5 ...

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... List of Chapters MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

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... FLASH Mass Erase Operation 2.6.4 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.5 FLASH Block Protection 2.6.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 1 General Description and DDA REFH Chapter 2 Memory and V ) ...

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... ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 BEMF Register 4.4 Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Chapter DDA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 REFH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 REFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 4 BEMF Counter Module (BEMF) Freescale Semiconductor ...

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... Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.4 Arithmetic/Logic Unit (ALU 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 5 Chapter 6 Chapter 7 Central Processor Unit (CPU) 9 ...

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... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.6 CONFIG Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.6.1 External Clock Enable (EXTCLKEN 8.6.2 External Crystal Enable (EXTXTALEN 8.6.3 Slow External Clock (EXTSLOW 8.6.4 Oscillator Enable In Stop (OSCENINSTOP MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Chapter 8 Freescale Semiconductor ...

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... LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.4 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 9 External Interrupt (IRQ) Chapter 10 Keyboard Interrupt (KBD) Module Chapter 11 Low-Voltage Inhibit (LVI) Module 11 ...

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... Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 13.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Chapter 12 Input/Output (I/O) Ports (PORTS) Chapter 13 Freescale Semiconductor ...

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... Program Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 14.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 14 System Integration Module (SIM) 13 ...

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... SPSCK (Serial Clock 183 15.12.4 SS (Slave Select 183 15.12.5 V (Clock Ground 184 SS 15.13 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.13.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.13.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.13.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Chapter 15 Freescale Semiconductor ...

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... TIMA Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.8.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 18.2 Features 209 18.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 16 Timebase Module (TBM) Chapter 17 Timer Interface A (TIMA) Module Chapter 18 Timer Interface B (TIMB) Module 15 ...

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... Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 19.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 19.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 19.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 19.3.1.6 Baud Rate 235 19.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 19.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Chapter 19 Development Support Freescale Semiconductor ...

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... QFP (Case Number 873 254 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 A.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 A.4 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 20 Electrical Specifications Chapter 21 Appendix A MC68HC908EY8 Glossary Revision History 17 ...

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... Table of Contents MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

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... Enhanced serial communications interface module (ESCI) for local interconnect network (LIN) connectivity • Serial peripheral interface (SPI security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor (1) 19 ...

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... Memory-to-memory data transfers Fast 8 × 8 multiply instruction • Fast 16 ÷ 8 divide instruction • • Binary-coded decimal (BCD) instructions • Optimization for controller applications • Third party C language support MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

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... ANALOG-TO-DIGITAL DDA CONVERTER MODULE V REFL V SSA V DD POWER V SS MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor INTERNAL BUS SINGLE BREAKPOINT BREAK MODULE 5-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE A 2-CHANNEL TIMER INTERFACE MODULE B ENHANCED SERIAL COMMUNICATION INTERFACE MODULE ...

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... C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Figure 1-2. Pin Assignments and PTE1/RxD 23 PTE0/TxD 22 PTC0/MISO 21 PTC1/MOSI 20 PTA5/SPSCK 19 PTA6/SS 18 PTB0/AD0 17 IRQ Figure 1-3 Freescale Semiconductor ...

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... ADC. V REFH same potential the low reference supply for the ADC. V REFL same potential as V See Chapter 3 Analog-to-Digital Converter (ADC) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor MCU 0.1 µ Figure 1-3. Power Supply Bypassing ...

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... MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev and Chapter 9 External Interrupt and and Chapter 12 Input/Output (I/O) Ports NOTE ). Although the I/O ports of the MC68HC908EY16 do not (IRQ). Chapter 17 Timer Interface A (TIMA) Chapter 12 Input/Output Module. (PORTS). and Chapter 12 Input/Output Freescale Semiconductor ...

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... BRKSCR • $FE0C; LVI status register, LVISR • $FF7E; FLASH block protect register, FLBPR • $FF80; ICG trim value (optional), ICGT Data registers are shown in Figure MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 2-2. and Table 2 list of vector locations. 25 ...

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... Locations $FFF6–$FFFD are reserved for eight security bytes. Figure 2-1. Memory Map LVI Status Register (LVISR) Reserved 3 Bytes Reserved 16 Bytes for A-Family Parts Monitor ROM 310 Bytes Unimplemented 40 Bytes ICG Trim Value (Optional) (ICGT) Unimplemented 93 Bytes FLASH Vectors 36 Bytes Freescale Semiconductor ...

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... Register E (DDRE) Write: See page 123. Reset: Read: BEMF Register $000B (BEMF) Write: See page 55. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Bit PTA6 PTA5 PTA4 Unaffected by reset PTB7 PTB6 PTB5 ...

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... Unaffected by reset R LINR SCP1 SCP0 PDS2 PDS1 PDS0 PSSB4 Unimplemented R = Reserved Bit CPHA SPWOM SPE SPTIE SPTE MODFEN SPR1 SPR0 WAKE ILTY PEN PTY RWU SBK ORIE NEIE FEIE PEIE BKF RPF SCR2 SCR1 SCR0 PSSB3 PSSB2 PSSB1 PSSB0 Unaffected Freescale Semiconductor ...

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... High (TACNTH) Write: See page 203. Reset: Read: Timer A Counter Register $0022 Low (TACNTL) Write: See page 203. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Bit ALOST AM1 AM0 ACLK ARD7 ...

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... TOV0 CH0MAX BIT 11 BIT 10 BIT 9 BIT 8 BIT 3 BIT 2 BIT 1 BIT 0 ELS1B ELS1A TOV1 CH1MAX BIT 11 BIT 10 BIT 9 BIT 8 BIT 3 BIT 2 BIT 1 BIT 0 R PS2 PS1 PS0 BIT 11 BIT 10 BIT 9 BIT BIT 3 BIT 2 BIT 1 BIT BIT 11 BIT 10 BIT 9 BIT Unaffected Freescale Semiconductor ...

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... Register (ICGDVR) Write: See page 99. Reset: Read: ICG DCO Stage Control $003A Register (ICGDSR) Write: See page 100. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Bit BIT 7 BIT 6 BIT 5 BIT CH0F ...

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... POR PIN COP ILOP BCFE BIT 15 BIT 14 BIT 13 BIT Unimplemented R = Reserved Bit ADCH3 ADCH2 ADCH1 ADCH0 AD9 AD8 AD3 AD2 AD1 AD0 0 MODE1 MODE0 SBSW NOTE ILAD MENRST LVI HVEN MASS ERASE PGM BIT 11 BIT 10 BIT 9 BIT Unaffected Freescale Semiconductor ...

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... Write: See page 41. Reset: 1. Non-volatile FLASH register. Read: COP Control Register $FFFF (COPCTL) Write: See page 63. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Bit BIT 7 BIT 6 BIT 5 BIT BRKE ...

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... TIMA channel 0 vector (low) $FFF8 CMIREQ (high) IF2 $FFF9 CMIREQ (low) $FFFA IRQ vector (high) IF1 $FFFB IRQ vector (low) $FFFC SWI vector (high) — $FFFD SWI vector (low) $FFFE Reset vector (high) — $FFFF Reset vector (low) Vector Freescale Semiconductor ...

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... In the 125°C to 135°C temperature range, the FLASH is guaranteed as read only security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE NOTE NOTE NOTE Register ...

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... This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation unselected MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev HVEN Bit 0 MASS ERASE PGM Freescale Semiconductor ...

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... Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE NOTE 19.3 Monitor Module ...

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... When in monitor mode, with security sequence failed (see stead of any FLASH address. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev (1) within the FLASH memory address range. NOTE NOTE 19.3.2 Security), write to the FLASH block protect register in- Freescale Semiconductor ...

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... Do not exceed t 1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing the PGM bit, must not exceed the maximum programming time, t MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor (Figure 2-4 NOTE ( programmed ...

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... SET HVEN BIT 6 WAIT FOR A TIME, t PGS 7 WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED 8 WAIT FOR A TIME, t PROG COMPLETED YES PROGRAMMING THIS ROW CLEAR PGM BIT WAIT FOR A TIME, t NVH CLEAR HVEN BIT WAIT FOR A TIME, t RCV END OF PROGRAMMING Freescale Semiconductor ...

Page 41

... With this mechanism, the protect start address can be $XX00, $XX40, $XX80, and $XXC0 (64 bytes page boundaries) within the FLASH memory. START ADDRESS OF FLASH BLOCK PROTECT Figure 2-6. FLASH Block Protect Start Address MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE ...

Page 42

... FFFF $FF40 (1111 1111 0100 0000) — $FFFF FLBPR and vectors are protected $FF80 (1111 1111 1000 0000) — FFFF Vectors are protected The entire FLASH memory is not protected. NOTE Freescale Semiconductor ...

Page 43

... An analog multiplexer allows the single ADC to select one of the 8 ADC channels as ADC voltage IN (ADCVIN). ADCVIN is converted by the successive approximation algorithm. When the conversion is completed, the ADC places the result in the ADC data register (ADRH and ADRL) and sets a flag or generates an interrupt. See MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Figure 3-2. 43 ...

Page 44

... PERIODIC WAKEUP TIMEBASE MODULE ARBITER MODULE PRESCALER MODULE BEMF MODULE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RxD PTE0/TxD POWER-ON RESET MODULE SECURITY MODULE Freescale Semiconductor ...

Page 45

... All other input voltages will result in $3FF if greater than V if less than V . REFL Input voltage should not exceed the analog supply voltages. See Analog-to-Digital Converter (ADC) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ADC DATA REGISTERS ADC VOLTAGE IN ADVIN ADC ADC CLOCK CLOCK ...

Page 46

... ADRH or else the interlocking will prevent all new conversions from being stored. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev to17 ADC Cycles ADC Frequency 16 to17 ADC Cycles = 8 to 8.5 µs 4 MHz/2 minimum and f ADIC 20.10 Analog-to-Digital Converter (ADC) maximum ADIC Freescale Semiconductor ...

Page 47

... When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit The COCO bit is not used as a conversion complete flag when interrupts are enabled. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE Figure 3-3. ...

Page 48

... V REFH pin to the same voltage potential DDA for good results. DDA pin to the same voltage potential SSA . Connect the V pin to the same REFH . See Chapter 20 Electrical REFH pin to the same voltage potential as REFL Specifications. , ANx, and grounding. REFL Freescale Semiconductor ...

Page 49

... ADC status and control register is written or whenever the ADC data register is read. If AIEN bit is 1, the COCO is a read/write bit. Reset clears this bit Conversion completed (AIEN = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor and V REFH REFL and V ...

Page 50

... Used for factory testing. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Table 3-1. NOTE NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 Input Select PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 Unused * Reserved ** Unused * V REFH V REFL ADC power off Freescale Semiconductor ...

Page 51

... Until ADRL is read, all subsequent ADC results will be lost. Address: $003D Bit 7 Read: 0 Write: Reset: Address: $003E Read: AD7 Write: Reset: Figure 3-6. ADC Data Register High (ADRH) and Low (ADRL) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented ...

Page 52

... MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev AD8 AD7 AD6 AD5 Unaffected by reset AD0 Unaffected by reset = Unimplemented Unaffected by reset AD8 AD7 AD6 AD5 Unaffected by reset = Unimplemented ADRH 2 1 Bit 0 AD4 AD3 AD2 ADRL ADRH 2 1 Bit ADRL AD4 AD3 AD2 Freescale Semiconductor ...

Page 53

... MODE1:MODE0 selects among four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified sign data mode MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Address ADIV1 ADIV0 ...

Page 54

... Analog-to-Digital Converter (ADC) Module MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

Page 55

... The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The BEMF module remains active after execution of the WAIT instruction. In WAIT mode the BEMF register is not accessible by the CPU. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 56

... PERIODIC WAKEUP TIMEBASE MODULE ARBITER MODULE PRESCALER MODULE BEMF MODULE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RxD PTE0/TxD POWER-ON RESET MODULE SECURITY MODULE Freescale Semiconductor ...

Page 57

... Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 5-2. Address: $001E Bit 7 Read: R ESCIBDSRC EXTXTALEN EXTSLOW EXTCLKEN TMBCLKSEL OSCENINSTOP SSBPUENB Write: Reset Reserved Figure 5-1. Configuration Register 2 (CONFIG2) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE Figure 5-1 and 2 1 Bit ...

Page 58

... External oscillator configured for an external clock OSC1 PTC3 source input (square wave) on OSC1 External oscillator configured for an external crystal configuration on OSC1 and OSC2. System will also OSC1 OSC2 operate with square-wave clock source in OSC1 Bit 0 (1) SSREC STOP COPD Description Freescale Semiconductor ...

Page 59

... When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP LVI enabled during stop mode 0 = LVI disabled during stop mode MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 8 Internal Clock Generator (ICG) Chapter 8 Internal Clock Generator Table 16-1 Chapter 8 Internal Clock Generator ...

Page 60

... COP module disabled 0 = COP module enabled MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Chapter 11 Low-Voltage Inhibit (LVI) Chapter 11 Low-Voltage Inhibit (LVI) Chapter 20 Electrical Specifications NOTE NOTE Chapter 6 Computer Operating Properly (COP) Module. Chapter 11 Low-Voltage Inhibit for the LVI’s voltage Module. Freescale Semiconductor ...

Page 61

... COP rate select bit, COPRS, in the CONFIG-1. When COPRS = 0, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to location $FFFF before MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER ...

Page 62

... The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 5 Configuration Registers (CONFIG1 and MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev NOTE TST NOTE Figure 6-1. 6.4 COP Control Register) clears the COP CONFIG2). . During the break state, Freescale Semiconductor ...

Page 63

... The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 6.8 COP Module During Break Interrupts The COP is disabled during a break interrupt when V MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor CONFIG2 ...

Page 64

... Computer Operating Properly (COP) Module MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

Page 65

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 65 ...

Page 66

... STACK POINTER (SP) 0 PROGRAM COUNTER (PC CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG Figure 7-1. CPU Registers Unaffected by reset Figure 7-2. Accumulator ( Figure 7-3. Index Register (H: Bit 0 Bit Freescale Semiconductor ...

Page 67

... The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 68

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev NOTE 2 1 Bit Freescale Semiconductor ...

Page 69

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Arithmetic/Logic Unit (ALU) 69 ...

Page 70

... EXT IX2 – IX1 SP1 9EE4 ff 4 SP2 9ED4 DIR INH 48 1 INH 58 1 – – IX1 SP1 9E68 ff 5 DIR INH 47 1 INH 57 1 – – IX1 SP1 9E67 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...

Page 71

... CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – – – – – – REL PC ← (PC rel ? IRQ = 0 – ...

Page 72

... DIR INH 4A 1 INH 5A 1 – – – IX1 SP1 9E6A ff 5 INH 52 7 IMM DIR EXT IX2 – IX1 SP1 9EE8 ff 4 SP2 9ED8 DIR INH 4C 1 INH 5C 1 – – – IX1 SP1 9E6C ff 5 Freescale Semiconductor ...

Page 73

... ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL); SP ← (SP) – 1 – ...

Page 74

... IX2 IX1 SP1 9EE2 ff 4 SP2 9ED2 DIR EXT IX2 – IX1 SP1 9EE7 ff 4 SP2 9ED7 – DIR DIR EXT IX2 – IX1 SP1 9EEF ff 4 SP2 9EDF IMM DIR EXT IX2 IX1 SP1 9EE0 ff 4 SP2 9ED0 Freescale Semiconductor ...

Page 75

... Memory location N Negative bit 7.8 Opcode Map See Table 7-2. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← (SP) – 1; Push (CCR) SP ← ...

Page 76

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 77

... Functional Description The ICG, shown in Figure 8-2, contains these major submodules: • Clock enable circuit • Internal clock generator • External clock generator • Clock monitor circuit • Clock selection circuit MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE 77 ...

Page 78

... PERIODIC WAKEUP TIMEBASE MODULE ARBITER MODULE PRESCALER MODULE BEMF MODULE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RxD PTE0/TxD POWER-ON RESET MODULE SECURITY MODULE Freescale Semiconductor ...

Page 79

... EXTCLKEN ECGON ICGON EXTXTALEN EXTSLOW INTERNAL LOGIC TO MCU EXTERNAL CONFIGURATION REGISTER BIT NAME TOP LEVEL SIGNAL NAME MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor CLOCK SELECTION CIRCUIT CLOCK MONITOR CIRCUIT INTERNAL CLOCK GENERATOR CLOCK/PIN ENABLE CIRCUIT EXTERNAL CLOCK GENERATOR PTC4 ...

Page 80

... A frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators • A digital loop filter MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Figure 8-3, creates a low frequency base clock (IBASE), which ) of 307.2 kHz ± 25 percent, and an internal clock (ICLK) which is NOM Freescale Semiconductor ...

Page 81

... The frequency comparator effectively compares the low-frequency base clock (IBASE nominal frequency First, the frequency comparator converts IBASE to a voltage by charging a known NOM capacitor with a current reference for a period dependent on IBASE. This voltage is compared to a voltage MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ++ + DIGITAL LOOP FILTER – ...

Page 82

... Minimum $xF7 to $xFF Maximum $x00 to $x08 Minimum $xDF to $xFF Maximum $x00 to $x20 Relative Correction in DCO –2/31 –6.45% –2/19 –10.5% –0.5/31 –1.61% –0.5/17.5 –2.86% –0.0625/31 –0.202% –0.366% +0.202% +0.0625/17 +0.368% +0.5/30.5 +1.64% +0.5/17 +2.94% +2/29 +6.90% +2/17 +11.8% Freescale Semiconductor ...

Page 83

... S be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information.) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Circuit) and indicates that the external clock function is desired. When EXTERNAL CLOCK GENERATOR ...

Page 84

... ICGON EXTXTALEN REFERENCE GENERATOR EXTSLOW ECGS ECLK ECGEN ESTBCLK IREF ECLK ECGEN ACTIVITY DETECTOR ECLK CMON CONFIGURATION REGISTER BIT TOP LEVEL SIGNAL IOFF IOFF ICGS ICGS EREF ESTBCLK IREF ECGS ECGS EOFF EOFF NAME REGISTER BIT NAME MODULE SIGNAL Freescale Semiconductor ...

Page 85

... ICGS is cleared when FICGS is clear, the internal clock generator is turned off stop mode (ICGEN is clear), or when IOFF is set. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE Figure 8-6, looks for at least one falling edge on the ...

Page 86

... TOP LEVEL SIGNAL Figure 8-7, looks for at least one falling edge on the external DFFRS DFFRR CONFIGURATION REGISTER BIT TOP LEVEL SIGNAL IOFF ICGS DFFRR CK R REGISTER BIT NAME NAME MODULE SIGNAL EOFF EGGS NAME REGISTER BIT NAME MODULE SIGNAL Freescale Semiconductor ...

Page 87

... Then the output starts switching at the new clock’s frequency. This transition guarantees that no glitches will be seen on the output even though the select input may change MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Figure 8-8, contains two clock switches which generate the oscillator ...

Page 88

... A short assembly code example of how to employ this flow is shown in Figure 8-9. This code is for illustrative purposes only and does not represent valid syntax for any particular assembler. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

Page 89

... Figure 8-10. Code Example for Enabling the Clock Monitor MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ;Clock Monitor Enabling Code Example ;This code turns on both clocks, selects the desired ; one, then turns on the Clock Monitor and Interrupts ;Mask for CMIE, CMON, ICGON, ICGS, ECGON, ECGS ...

Page 90

... The dependence of this error on the DDIV[3:0] value and the number of cycles the error is measured over is shown in Table MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev 8-2. Freescale Semiconductor ...

Page 91

... Likewise, when DSTG[4:0] is %11111, the ring operates at 25 stage delays for cycles and at 23 stage delays for one of 32 cycles. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Table 8-2. Quantization Error in ICLK ICLK Cycles Bus Cycles 1 ...

Page 92

... Therefore, the total time it takes to double or halve the clock period is 44*N*τ MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev 8.4.1 Switching Clock 8.4.1 Switching Clock Sources), 8.4.2 Enabling the Clock Monitor), if desired. . The period of ICLK, however, will vary as the corrections occur. ICLK Sources). . ICLKFAST Freescale Semiconductor ...

Page 93

... Table 8-3. Typical Settling Time Examples τ (6.45 MHz) 1/ (25.8 MHz) 1/ (25.8 MHz) 1/ (307.2 kHz) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor –1)*44*N*τ , where x is the number of times the speed needs ICLKFAST ICLKSLOW ) minus the final clock period (τ 1 τ ...

Page 94

... ICGS) are cleared, which will enable the external clock stabilization divider upon recovery. The clock monitor is disabled (CMON = 0) which will also clear the clock monitor interrupt enable (CMIE) and clock monitor flag (CMF) bits. The CS, ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are unaffected. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Freescale Semiconductor ...

Page 95

... Hz to 307.2 kHz). When EXTSLOW is clear, the clock monitor will expect an external clock faster than the low-frequency base clock (307.2 kHz to 32 MHz). The default state for this option is clear. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Chapter 5 Configuration Registers (CONFIG1 and CONFIG Options 95 ...

Page 96

... Freescale Semiconductor — — — — — uw — uw — — — ...

Page 97

... ICGON is clear. This bit is forced clear when the clock monitor determines that the external clock (ECLK) is inactive, when ECGON is clear, or during reset External clock (ECLK) sources CGMXCLK 0 = Internal clock (ICLK) sources CGMXCLK MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor CMF ...

Page 98

... A value of $00 in this register is interpreted the same as a value of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal 21) for default frequency of 6.45 MHz ± 25 percent (1.613 MHz ± 25 percent bus). MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev Bit Freescale Semiconductor ...

Page 99

... When ICGON is set, DDIV is controlled by the digital loop filter. The range of valid values for DDIV is from $0 to $9. Values of $A through $F are interpreted the same as $9. Since the DCO is active during reset, reset has no effect on DSTG and the value may vary. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 100

... ICGON is set to prevent inadvertent frequency shifting. When ICGON is set, DSTG is controlled by the digital loop filter. Since the DCO is active during reset, reset has no effect on DSTG and the value may vary. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 100 DSTG6 DSTG5 DSTG4 DSTG3 Unaffected by reset 2 1 Bit 0 DSTG2 DSTG1 DSTG0 Freescale Semiconductor ...

Page 101

... Functional Description A logic 0 applied to the external interrupt pin can latch a central processor unit (CPU) interrupt request. Figure 9-1 shows the structure of the IRQ module. ACK VECTOR FETCH DECODER IRQ MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor V DD CLR IRQ LATCH IMASK MODE Figure 9-1 ...

Page 102

... IRQ pin is at logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 102 NOTE Figure 9-2. Freescale Semiconductor ...

Page 103

... IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor FROM RESET I BIT SET? NO YES ...

Page 104

... This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 104 IRQF Reserved 2 1 Bit 0 0 IMASK MODE ACK Freescale Semiconductor ...

Page 105

... If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE4 and $FFE5. • Return of all enabled keyboard interrupt pins to logic 1. As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 105 ...

Page 106

... PERIODIC WAKEUP TIMEBASE MODULE ARBITER MODULE PRESCALER MODULE BEMF MODULE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RxD PTE0/TxD POWER-ON RESET MODULE SECURITY MODULE Freescale Semiconductor ...

Page 107

... Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must for software to read the pin. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ACKK V DD RESET ...

Page 108

... To protect the KEYF bit during the break state, write the BCFE bit. With BCFE at 0, writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. See 10.7.1 Keyboard Status and Control MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 108 Register. Freescale Semiconductor ...

Page 109

... MODEK — Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 110

... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register KBDx pin enabled as keyboard interrupt pin 0 = KBDx pin not enabled as keyboard interrupt pin MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 110 KBIE4 KBIE3 Bit 0 KBIE2 KBIE1 KBIE0 Freescale Semiconductor ...

Page 111

... Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to continue monitoring the voltage level while in stop mode LOW V DD DETECTOR LVI5OR3 FROM CONFIG-1 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor voltage falls to the LVI trip voltage. DD STOP INSTRUCTION FROM CONFIG-1 LVIRSTD LVIPWRD FROM CONFIG-1 V > LVI = 0 DD ...

Page 112

... LVI LVI TRIPF DD TRIPR rises above a voltage, LVI TRIPR 11.3.2 Forced Reset level, software can monitor V level, enabling LVI resets allows the LVI Table 11-1). Please refer level . 2 1 Bit voltage. (See TRIPF LVIOUT 0 1 Previous Value Freescale Semiconductor . V must ...

Page 113

... LVI module will be active after a STOP instruction. With the LVIPWRD bit in the configuration register programmed to 1, and the LVISTOP bit programmed the LVI module will be inactive after a STOP instruction. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor LVI Interrupts 113 ...

Page 114

... Low-Voltage Inhibit (LVI) Module MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 114 Freescale Semiconductor ...

Page 115

... Data Direction Register A Data direction register A determines whether each port A pin is an input or an output. Writing DDRA bit enables the output buffer for the corresponding port A pin disables the output buffer. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE 6 5 ...

Page 116

... Figure 12-3. Port A I/O Circuit Table 12-1 summarizes the operation of the port A pins. Table 12-1. Port A Pin Functions Accesses to DDRA I/O Pin Mode Read/Write Input, Hi-Z DDRA[6:0] Output DDRA[6: Bit 0 DDRA2 DDRA1 DDRA0 PTAx Accesses to PTA Read Write (1) Pin PTA[6:0] PTA[6:0] PTA[6:0] Freescale Semiconductor ...

Page 117

... Data direction register B (DDRB) does not affect the data direction of port B pins that are being used by the TIMB. However, the DDRB bits always determine whether reading port B returns the states of the latches or the states of the pins. See MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor PTB6 ...

Page 118

... Figure 12-6. Port B I/O Circuit summarizes the operation of the port B pins. Table 12-2. Port B Pin Functions Accesses to DDRB I/O Pin Mode Read/Write Input, Hi-Z DDRB[7:0] Output DDRB[7: Bit 0 DDRB2 DDRB1 DDRB0 PTBx Accesses to PTB Read Write (1) Pin PTB[7:0] PTB[7:0] PTB[7:0] Freescale Semiconductor ...

Page 119

... Figure 12-8. Data Direction Register C (DDRC) MCLKEN — MCLK Enable Bit This read/write bit enables MCLK output signal on PTC2. If MCLK is enabled, PTC2 is under the control of MCLKEN. Reset clears this bit MCLK output enabled 0 = MCLK output disabled MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor PTC4 ...

Page 120

... C pins. Table 12-3. Port C Pin Functions Accesses to DDRC I/O Pin Mode Read/Write Input, Hi-Z DDRC[7] Output DDRC[7] Input, Hi-Z DDRC[4:0] Output DDRC[4:0] PTCx Accesses to PTC Read Write Pin PTC2 0 — (1) Pin PTC[4:0] PTC[4:0] PTC[4:0] Freescale Semiconductor ...

Page 121

... These read/write bits control port D data direction. Reset clears DDRD[1:0], configuring all port D pins as inputs Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 122

... D pins. Table 12-4. Port D Pin Functions Accesses to DDRD I/O Pin Mode Read/Write Input, Hi-Z DDRD[1:0] Output DDRD[1: Unaffected by reset = Unimplemented PTDx Accesses to PTD Read Write (1) Pin PTD[1:0] PTD[1:0] PTD[1: Bit PTE1 PTE0 RXD TXD Freescale Semiconductor ...

Page 123

... These read/write bits control port E data direction. Reset clears DDRE[1:0], configuring all port E pins as inputs Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 1. 1. NOTE Table 12-5. 6 ...

Page 124

... PTEx Figure 12-15. Port E I/O Circuit Table 12-5 summarizes the operation of the port E pins. Table 12-5. Port E Pin Functions Accesses to DDRE I/O Pin Mode Read/Write Input, Hi-Z DDRE[1:0] Output DDRE[1:0] PTEx Accesses to PTE Read Write (1) Pin PTE[1:0] PTE[1:0] PTE[1:0] Freescale Semiconductor ...

Page 125

... Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection 13.3 Pin Name Conventions The generic names of the ESCI input/output (I/O) pins are: • RxD (receive data) • TxD (transmit data) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 125 ...

Page 126

... Table 13-1. Pin Name Conventions RxD PTE1/RxD PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RxD PTE0/TxD POWER-ON RESET MODULE SECURITY MODULE TxD PTE0/TxD Freescale Semiconductor ...

Page 127

... WAKEUP CONTROL BUS CLOCK Enhanced PRE- CGMXCLK SCALER ÷ 4 SCALER SL SL=1 -> SCI_CLK = BUSCLK SL=0 -> SCI_CLK = CGMXCLK (4x BUSCLK) Figure 13-2. ESCI Module Block Diagram MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor INTERNAL BUS LOOPS RECEIVE FLAG CONTROL CONTROL BKF ENSCI RPF ...

Page 128

... TXINV M PARITY GENERATION T8 SCTE SCTE SCTIE SCTIE TC TC TCIE TCIE Figure 13-4. ESCI Transmitter Figure 13-3. NEXT START BIT STOP BIT PARITY OR DATA NEXT BIT START BIT BIT 8 STOP BIT SCI_TxD TRANSMITTER CONTROL LOGIC SBK LOOPS ENSCI TE LINT Freescale Semiconductor ...

Page 129

... When LINR is set in SCBR, the ESCI recognizes a break character when a start bit is followed consecutive 0 data bits and a 0 where the stop bit should be, resulting in a total consecutive 0 data bits. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Functional Description 129 ...

Page 130

... Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 130 NOTE Freescale Semiconductor ...

Page 131

... RPF PDS1 PDS0 M PSSB4 WAKE PSSB3 ILTY PSSB2 PSSB1 PEN PSSB0 PTY Figure 13-5. ESCI Receiver Block Diagram MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor INTERNAL BUS SCR1 SCR2 SCR0 BAUD ÷ 16 DIVIDER DATA H RECOVERY ALL ZEROS WAKEUP LOGIC PARITY ...

Page 132

... When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. RxD SAMPLES RT CLOCK RT CLOCK STATE RT CLOCK RESET MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 132 START BIT START BIT START BIT DATA QUALIFICATION VERIFICATION SAMPLING Figure 13-6. Receiver Data Sampling LSB Freescale Semiconductor ...

Page 133

... To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. summarizes the results of the stop bit samples. RT8, RT9, and RT10 Samples MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Table 13-2. Start Bit Verification Start Bit Verification 000 ...

Page 134

... STOP DATA SAMPLES Figure 13-7. Slow Data Figure 13-7, the receiver counts 154 RT cycles at the point 154 147 – × 100 = 4.54% ------------------------- - 154 Figure 13-7, the receiver counts 170 RT cycles at the point 170 163 – × 100 = 4.12% ------------------------- - 170 Freescale Semiconductor ...

Page 135

... Idle input line condition — When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor STOP IDLE OR NEXT CHARACTER ...

Page 136

... WAIT instruction. 13.5.2 Stop Mode The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 136 NOTE Freescale Semiconductor ...

Page 137

... ESCI data register, SCDR • ESCI baud rate register, SCBR • ESCI prescaler register, SCPSC • ESCI arbiter control register, SCIACTL • ESCI arbiter data register, SCIADAT MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor (BRK). ESCI During Break Module Interrupts 137 ...

Page 138

... Table 13-5).The ninth bit can serve as a receiver wakeup signal parity bit. Reset clears the M bit 9-bit ESCI characters 0 = 8-bit ESCI characters MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 138 ENSCI TXINV M WAKE NOTE 2 1 Bit 0 ILTY PEN PTY Freescale Semiconductor ...

Page 139

... Reset clears the PTY bit Odd parity 0 = Even parity Changing the PTY bit in the middle of a transmission or reception can generate a parity error. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Table 13-5. Character Format Selection Character Format Start Bits Data Bits Parity ...

Page 140

... This read/write bit enables the IDLE bit to generate ESCI receiver CPU interrupt requests. Reset clears the ILIE bit IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 140 TCIE SCRIE ILIE Bit 0 RE RWU SBK Freescale Semiconductor ...

Page 141

... No break characters being transmitted Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the ESCI to send a break character instead of a preamble. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE NOTE NOTE I/O Registers ...

Page 142

... This read/write bit enables ESCI error CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE ESCI error CPU interrupt requests from PE bit enabled 0 = ESCI error CPU interrupt requests from PE bit disabled MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 142 ORIE Unimplemented R = Reserved 2 1 Bit 0 NEIE FEIE PEIE Unaffected Freescale Semiconductor ...

Page 143

... This clearable, read-only bit is set when consecutive 1s appear on the receiver input. IDLE generates an ESCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 144

... READ SCS1 SCRF = 1 SCRF = READ SCDR BYTE 1 BYTE 2 DELAYED FLAG CLEARING SEQUENCE BYTE 2 BYTE 3 READ SCS1 SCRF = READ SCDR BYTE 1 Figure 13-13. Flag Clearing Sequence BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = READ SCDR BYTE 3 Freescale Semiconductor ...

Page 145

... Polling RPF before disabling the ESCI module or entering stop mode can show whether a reception is in progress Reception in progress reception in progress MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 146

... LINR SCP1 SCP0 Reserved Table 13-6. Reset clears LINR. Table 13-6. ESCI LIN Control Bits M Functionality X Normal ESCI functionality 0 13-bit break detect enabled for LIN receiver 1 14-bit break detect enabled for LIN receiver 2 1 Bit Bit 0 SCR2 SCR1 SCR0 Freescale Semiconductor ...

Page 147

... Bit 7 Read: PDS2 Write: Reset: 0 Figure 13-17. ESCI Prescaler Register (SCPSC) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Table 13-7. ESCI Baud Rate Prescaling Baud Rate Register Prescaler Divisor (BPD Table 13-8. ESCI Baud Rate Selection Baud Rate Divisor (BD) ...

Page 148

... MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 148 NOTE Table 13-9. ESCI Prescaler Division Ratio Prescaler Divisor (PD Bypass this prescaler Frequency of the SCI clock source 64 x BPD (PD + PDFA) or CGMXCLK (selected by Bus Table 13-9. Reset clears PDS2–PDS0 Table 13-10. Reset clears Freescale Semiconductor ...

Page 149

... MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Prescaler Divisor Fine Adjust (PDFA) 0/ 1/32 = 0.03125 2/32 = 0.0625 3/32 = 0.09375 4/32 = 0.125 5/32 = 0.15625 6/32 = 0.1875 7/32 = 0.21875 8/32 = 0.25 9/32 = 0.28125 10/32 = 0.3125 11/32 = 0.34375 12/32 = 0.375 13/32 = 0.40625 14/32 = 0.4375 15/ ...

Page 150

... Freescale Semiconductor ...

Page 151

... AFIN— Arbiter Bit Time Measurement Finish Flag This read-only bit indicates bit time measurement has finished. Clear AFIN by writing any value to SCIACTL. Reset clears AFIN Bit time measurement has finished 0 = Bit time measurement not yet finished MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ALOST ...

Page 152

... ESCI module, internal chip signal), the counter is started. When the counter reaches $38 (ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed this case, RxD is sensed low (for example, MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 152 ARD6 ARD5 ARD4 ARD3 Unimplemented 2 1 Bit 0 ARD2 ARD1 ARD0 Figure 13-21). A logic 0 Freescale Semiconductor ...

Page 153

... Figure 13-20. Bit Time Measurement with ACLK = 0 RXD Figure 13-21. Bit Time Measurement with ACLK = 1, Scenario A RXD Figure 13-22. Bit Time Measurement with ACLK = 1, Scenario B MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor MEASURED TIME MEASURED TIME MEASURED TIME ESCI Arbiter 153 ...

Page 154

... Enhanced Serial Communications Interface (ESCI) Module MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 154 Freescale Semiconductor ...

Page 155

... The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in originates from either an external oscillator or from the internal clock generator. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Figure 14-1. Table 14-1. Signal Name Conventions ...

Page 156

... CGMOUT (FROM ICG) INTERNAL CLOCKS FORCED MON MODE ENTRY (FROM MENRST MODULE) LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE) INTERRUPT SOURCES CPU INTERFACE SIM COUNTER ÷ BUS CLOCK 2 GENERATORS SIM Freescale Semiconductor ...

Page 157

... Figure 14-3 IRL CGMOUT RST IAB PC MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 14.6.2 Stop Mode. and 14.7.2 SIM Reset Status Register. shows the relative timing. Figure 14-3. External Reset Timing Reset and System Initialization VECT H ...

Page 158

... ILLEGAL ADDRESS RESET ILLEGAL OPCODE RESET COP RESET INTERNAL RESET LVI POR MENRST Figure 14-4. Sources of Internal Reset Table 14-2. Reset Recovery Timing Actual Number of Cycles 4163 (4096 + ( RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 14-5. Internal Reset Timing VECTOR HIGH Freescale Semiconductor ...

Page 159

... When the MCU comes out of reset forced into monitor mode. See 19.3 Monitor Module (MON). MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 32 CYCLES Figure 14-6. POR Recovery while the MCU is in monitor mode. The COP ...

Page 160

... Normal, sequential program execution can be changed in two ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 160 voltage falls to the V DD Module. 14.3.2 Active Resets from Internal Sources TRIPF rises DD for Freescale Semiconductor ...

Page 161

... CPU uses to determine which vector to fetch. As shown in Figure 14-9, once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the I bit is cleared. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Figure 14-8 shows interrupt recovery timing. SP – – – ...

Page 162

... I BIT SET? I BIT SET? NO YES IRQ INTERRUPT ? NO YES ICG CLK MON INTERRUPT ? NO OTHER YES INTERRUPTS ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT VECTOR FETCH NEXT SWI YES ? NO RTI YES UNSTACK CPU REGISTERS INSTRUCTION ? NO EXECUTE INSTRUCTION Figure 14-9. Interrupt Processing SET I BIT Freescale Semiconductor ...

Page 163

... A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. 14.5.2 Reset All reset sources always have higher priority than interrupts and cannot be arbitrated. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor CLI LDA #$FF PSHH INT1 INTERRUPT SERVICE ROUTINE ...

Page 164

... Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 164 (BRK). The SIM puts the CPU into the break state by WAIT ADDR + 1 SAME NEXT OPCODE Figure 14-11. Wait Mode Entry Timing SAME SAME SAME Freescale Semiconductor ...

Page 165

... SSREC bit. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery then used to time the recovery period. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor show the timing for WAIT recovery. $DE0C $00FF ...

Page 166

... Figure 14-14. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 Table 14-3 shows the mapping of these registers. Table 14-3. SIM Registers Register SBSR SRSR SBFCR Reserved SAME SAME SAME SP SP – – – 3 Access Mode User User User 2 1 Bit 0 SBSW R R (1) Note Freescale Semiconductor ...

Page 167

... MENRST — Forced Monitor Mode Entry Reset Bit 1 = Last reset was caused by the MENRST circuit 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset was caused by the LVI circuit 0 = POR or read of SRSR MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor PIN COP ...

Page 168

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 168 Reserved 2 1 Bit Freescale Semiconductor ...

Page 169

... SPI I/O pins. The generic pin names appear in the text that follows. SPI Generic Pin Name Full SPI Pin Name MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Table 15-1. Pin Name Conventions MISO MOSI PTC0/MISO ...

Page 170

... PERIODIC WAKEUP TIMEBASE MODULE ARBITER MODULE PRESCALER MODULE BEMF MODULE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RxD PTE0/TxD POWER-ON RESET MODULE SECURITY MODULE Freescale Semiconductor ...

Page 171

... CLOCK DIVIDER ÷ 32 ÷ 128 CLOCK SPMSTR SPE SELECT SPR1 TRANSMITTER CPU INTERRUPT REQUEST RECEIVER/ERROR CPU INTERRUPT REQUEST MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor Table 15-2. I/O Register Addresses Register Name INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER ...

Page 172

... MCU must be at logic 0. SS must remain low until the transmission is complete. (See Mode Fault Error.) MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 172 NOTE 15.13.1 SPI Control MISO MISO MOSI MOSI SPSCK SPSCK Table Register.) Through the SPSCK pin, the baud rate generator of the Register. SLAVE MCU SHIFT REGISTER 15-3). 15.6.2 Freescale Semiconductor ...

Page 173

... Before writing to the CPOL bit or the CPHA bit (SPCR), disable the SPI by clearing the SPI enable bit (SPE). MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 15.5 Transmission Formats.) NOTE NOTE ...

Page 174

... This format may be preferable in systems having only one master and only one slave driving the MISO data line. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 174 BIT 6 BIT 5 BIT 4 BIT 3 BIT 6 BIT 5 BIT 4 BIT 3 15.6 BIT 2 BIT 1 LSB BIT 2 BIT 1 LSB 15.6.2 Freescale Semiconductor ...

Page 175

... SPI bit time. That is, the maximum delay between the write to SPDR and the start of the SPI transmission is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 176

... SCK = INTERNAL CLOCK ÷ 2; EARLIEST LATEST 2 POSSIBLE START POINTS SCK = INTERNAL CLOCK ÷ 8; EARLIEST 8 POSSIBLE START POINTS SCK = INTERNAL CLOCK ÷ 32; EARLIEST 32 POSSIBLE START POINTS SCK = INTERNAL CLOCK ÷ 128; EARLIEST 128 POSSIBLE START POINTS BIT 6 BIT LATEST LATEST LATEST Freescale Semiconductor ...

Page 177

... SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions will complete with an SPRF interrupt. avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit (SPSCR). MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor BYTE 2 BYTE 3 4 ...

Page 178

... CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. SPTE SPTIE SPE SPRIE SPRF BYTE Figure 15-9 not possible to enable SPI TRANSMITTER CPU INTERRUPT REQUEST SPI RECEIVER/ERROR CPU INTERRUPT REQUEST Freescale Semiconductor ...

Page 179

... To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing procedure must occur with no MODF condition existing or else the flag will not be cleared. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE NOTE 15.5 Transmission Formats ...

Page 180

... MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 180 Table 15-3. SPI Interrupts Request SPI Transmitter CPU Interrupt Request (SPTIE = 1) SPI Receiver CPU Interrupt Request (SPRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = 1) Figure 15-10 Freescale Semiconductor ...

Page 181

... SPI has been disabled. The user can disable the SPI by writing the SPE bit. The SPI also can be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 3 5 ...

Page 182

... The SPI module has four I/O pins and shares three of them with a parallel I/O port. • MISO — Data received • MOSI — Data transmitted • SPSCK — Serial clock • SS — Slave select • V — Clock ground SS MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 182 15.7 Interrupts.) 19.2.1.1 Flag Protection During Break Interrupts.) Freescale Semiconductor ...

Page 183

... CPHA = 1 format. See MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 2 C) capability (requiring software support master peripherals, MOSI becomes an open-drain output 2 C communication, the MOSI and MISO pins 2 C peripheral and through a pullup resistor to V ...

Page 184

... Table 15-4. SPI Configuration SPI Configuration X Not Enabled General-Purpose I/O; SS Ignored by SPI X Slave 0 Master without MODF General-Purpose I/O; SS Ignored by SPI 1 Master with MODF 15.13.2 SPI Status and Control 15.6.2 Mode Fault Error.) For the state of State of SS Logic Input-Only to SPI Input-Only to SPI Freescale Semiconductor ...

Page 185

... SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor ...

Page 186

... This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset clears the ERRIE bit MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 186 OVRF MODF SPTE ERRIE Bit 0 MODFEN SPR1 SPR0 Freescale Semiconductor 15.9 ...

Page 187

... For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. (See Fault Error). MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE Select)). I/O Registers 15.6.2 Mode ...

Page 188

... MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 188 Baud Rate Divisor (BD 128 CGMOUT Baud rate = ------------------------- - × Figure 15 Indeterminate after Reset Figure 15-14. SPI Data Register (SPDR) NOTE Table 15-5. SPR1 and Module Bit Freescale Semiconductor ...

Page 189

... OSCENINSTOP bit in the configuration register. The timebase module can be used in this mode to generate a periodic wakeup from stop mode. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE Figure 16-1, starts 189 ...

Page 190

... CPU interrupt request. Interrupts must be acknowledged by writing the TACK bit. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 190 DIVIDE BY 128 PRESCALER ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ 2 ÷ Figure 16-1. Timebase Block Diagram 0 1 TBON TBMINT TBIF TBIE R Freescale Semiconductor ...

Page 191

... The timebase module may remain active after execution of the STOP instruction if the internal clock generator has been enabled to operate during stop mode through the OSCENINSTOP bit in the configuration register. The timebase module can be used in this mode to generate a periodic wake up from stop mode. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 1 Divider t = ...

Page 192

... Reset clears the TBON bit Timebase is enabled Timebase is disabled and the counter initialized to 0s. Clearing TBON has no effect on the TBIF flag. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 192 TBR2 TBR1 TBR0 TACK Unimplemented R NOTE NOTE 2 1 Bit 0 TBIE TBON Reserved Freescale Semiconductor ...

Page 193

... TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter value at any time without affecting the counting sequence. The two TIMA channels are programmable independently as input capture or output compare channels. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor 193 ...

Page 194

... PERIODIC WAKEUP TIMEBASE MODULE ARBITER MODULE PRESCALER MODULE BEMF MODULE PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO PTD1/TACH1 PTD0/TACH0 PTE1/RxD PTE0/TxD POWER-ON RESET MODULE SECURITY MODULE Freescale Semiconductor ...

Page 195

... CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor PRESCALER SELECT PS2 ...

Page 196

... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 196 17.8.5 TIMA Channel Registers). Because Freescale Semiconductor 17.3.3 ...

Page 197

... TIMA to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to set the pin if the state of the PWM pulse is logic 0. OVERFLOW PTDx/TCHx Figure 17-3. PWM Period and Pulse Width MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE OVERFLOW PERIOD PULSE WIDTH ...

Page 198

... PWM period. At each subsequent overflow, the TIMA channel registers ( that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 198 17.8.1 TIMA Status and Control NOTE Register). 17.3.4 Pulse Width Freescale Semiconductor ...

Page 199

... The result duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 17.8.4 TIMA Channel Status and Control MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 Freescale Semiconductor NOTE Table 17-2. Table 17-2. ...

Page 200

... If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE After the break, doing the second step clears the status bit. MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10 200 Freescale Semiconductor ...

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