R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 120

• Manufacturer Part Number: R5F21272SNFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21272SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 10.15
10.5.3.3
mode
Stop
Interrupt
request
generated
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 10.15 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit
to 1.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is
generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
stability time
Sep 26, 2008
Internal
150 µs
(max.)
power
T0
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used
for exiting stop mode to 000b (interrupt disabled).
(flash memory operates)
(flash memory stops)
Exiting Stop Mode
Time from Stop Mode to Interrupt Routine Execution
FMR0 Register
FMSTP Bit
Oscillation time of
CPU clock source
used immediately
before stop mode
0
1
T1
Page 101 of 453
× 12 cycles + 30 µs (max.)
Time until Flash Memory
Period of system clock
Period of system clock
activation sequence
is Activated (T2)
Flash memory
× 12 cycles
T2
Time until CPU Clock
Period of CPU clock
CPU clock restart
is Supplied (T3)
Same as above
× 6 cycles
sequence
T3
Period of CPU clock
Interrupt sequence
Time for Interrupt
Same as above
Sequence (T4)
× 20 cycles
T4
10. Clock Generation Circuit
Following total
time of T0 to T4 is
the time from stop
mode until an
interrupt handling
is executed.
Remarks