R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 159

IC R8C/27 MCU FLASH 32LQFP

R5F21272SNFP#U0

Manufacturer Part Number
R5F21272SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
13.2
Table 13.3
NOTES:
Count source
Count operation
Period
Count start condition
Reset condition of watchdog
timer
Count stop condition
Operation at time of underflow
Registers, bits
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 13.3 lists the Specifications of Watchdog Timer (with Count Source Protection Mode Enabled).
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
0FFFFh with a flash programmer.
CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address
0FFFFh with a flash programmer.
Count Source Protection Mode Enabled
Sep 26, 2008
Item
Specifications of Watchdog Timer (with Count Source Protection Mode Enabled)
Page 140 of 453
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (4096)
Example: Period is approximately 32.8 ms when the low-speed on-chip
The WDTON bit
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
• When the WDTON bit is set to 0 (watchdog timer starts automatically
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
None (The count does not stop in wait mode after the count starts. The
MCU does not enter stop mode.)
Watchdog timer reset (Refer to 5.7 Watchdog Timer Reset)
• When setting the CSPPRO bit in the CSPR register to 1 (count source
• The following conditions apply in count source protection mode
Low-speed on-chip oscillator clock
reset)
after reset)
protection mode is enabled)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
The watchdog timer and prescaler start counting automatically after a
reset
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
- Writing to the CM10 bit in the CM1 register is disabled (It remains
- Writing to the CM14 bit in the CM1 register is disabled (It remains
oscillator on)
reset when watchdog timer underflows)
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
oscillator clock frequency is 125 kHz
(1)
in the OFS register (0FFFFh) selects the operation
Specification
(2)
, the following are set automatically
13. Watchdog Timer

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