R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 382

• Manufacturer Part Number: R5F21272SNFP#U0
• Description: IC R8C/27 MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/27r

Specifications of R5F21272SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 19.7
Flash Memory Control Register 4
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
0
To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1.
This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing
an erase command and completing the erase. (This bit is set to 0 during periods other than the above.)
In EW0 mode, it can be set to 0 or 1 by a program.
In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase
operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten).
The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled
until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the
above.)
In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.
In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming
w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program.
In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er-consumption read mode.
Sep 26, 2008
b3 b2
FMR4 Register
b1 b0
Bit Symbol
Symbol
FMR46
FMR47
FMR40
FMR41
FMR42
FMR43
FMR44
FMR4
(b5)
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—
Erase-suspend function
enable bit
Erase-suspend request bit
Program-suspend request bit
Erase command flag
Program command flag
Reserved bit
Read status flag
Low -pow er consumption read
mode enable bit
(1)
Address
Bit Name
01B3h
(1, 4, 5)
(2)
(3)
0 : Disable
1 : Enable
0 : Erase restart
1 : Erase-suspend request
0 : Program restart
1 : Program-suspend request
0 : Erase not executed
1 : Erase execution in progress
0 : Program not executed
1 : Program execution in progress
Set to 0.
0 : Disables reading
1 : Enables reading
0 : Disable
1 : Enable
After Reset
01000000b
Function
19. Flash Memory
RW
RW
RW
RW
RW
RO
RO
RO
RO