R5F21272SNFP#U0 Renesas Electronics America, R5F21272SNFP#U0 Datasheet - Page 60

IC R8C/27 MCU FLASH 32LQFP

R5F21272SNFP#U0

Manufacturer Part Number
R5F21272SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21272SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 6.9
Voltage Monitor 0 Circuit Control Register
b7 b6 b5 b4
NOTES:
1.
2.
3.
4. The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW0C register.
The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage
monitor 2 reset.
The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit
enabled). Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).
Sep 26, 2008
b3 b2
0
VW0C Register (For N, D Version Only)
b1 b0
Bit Symbol
VW0C0
VW0C2
VW0C6
VW0C7
VW0C1
VW0F0
VW0F1
Symbol
VW0C
(b3)
Page 41 of 453
Voltage monitor 0 reset
enable bit
Voltage monitor 0 digital filter
disable mode select bit
Reserved bit
Reserved bit
Sampling clock select bits
Voltage monitor 0 circuit
mode select bit
Voltage monitor 0 reset
generation condition select
bit
(4)
(3)
Address
Bit Name
0038h
(1)
b5 b4
0 0 : fOCO-S divided by 1
0 1 : fOCO-S divided by 2
1 0 : fOCO-S divided by 4
1 1 : fOCO-S divided by 8
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is set
to 0, and hardw are reset
0 : Disable
1 : Enable
0 : Digital filter enabled mode
1 : Digital filter disabled mode
Set to 0.
When read, the content is undefined.
When the VW0C0 bit is set to 1 (voltage monitor 0
reset enabled), set to 1.
When the VW0C1 bit is set to 1 (digital filter
disabled mode), set to 1.
(digital filter circuit enabled)
(digital filter circuit disabled)
Function
After Reset
6. Voltage Detection Circuit
(2)
: 0000X000b
: 0100X001b
RW
RW
RW
RW
RW
RW
RW
RW
RO

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