R5F21275SDFP#U0 Renesas Electronics America, R5F21275SDFP#U0 Datasheet - Page 102

IC R8C/27 MCU FLASH 32LQFP

R5F21275SDFP#U0

Manufacturer Part Number
R5F21275SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21275SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Quantity
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Part Number:
R5F21275SDFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Part Number:
R5F21275SDFP#U0R5F21275SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
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Company:
Part Number:
R5F21275SDFP#U0R5F21275SDFP#X6
Manufacturer:
Renesas Electronics America
Quantity:
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 10.4
Oscillation Stop Detection Register
b7 b6 b5 b4
NOTES:
0 0 0 0
1.
2.
3.
4.
5.
6.
7.
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.
Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip
oscillator mode (XIN clock stops).
The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains
unchanged even w hen set to 0 (XIN clock selected).
The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled).
The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
Refer to Figure 10.18 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to XIN
Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
Sep 26, 2008
b3 b2 b1 b0
OCD Register
Bit Symbol
(b7-b4)
Symbol
OCD0
OCD1
OCD2
OCD3
OCD
Page 83 of 453
Oscillation stop detection enable
bit
Oscillation stop detection
interrupt enable bit
System clock select bit
Clock monitor bit
Reserved bits
(7)
(1)
Address
Bit Name
000Ch
(5, 6)
(4)
0 : Oscillation stop detection function
1 : Oscillation stop detection function
0 : Disabled
1 : Enabled
0 : Selects XIN clock
1 : Selects on-chip oscillator clock
0 : XIN clock oscillates
1 : XIN clock stops
Set to 0.
disabled
enabled
(2)
(2)
After Reset
00000100b
Function
(7)
10. Clock Generation Circuit
(3)
RW
RW
RW
RW
RW
RO

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