R5F21275SDFP#U0 Renesas Electronics America, R5F21275SDFP#U0 Datasheet - Page 460

IC R8C/27 MCU FLASH 32LQFP

R5F21275SDFP#U0

Manufacturer Part Number
R5F21275SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21275SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
21.5
21.5.1
21.5.2
21.5.2.1
21.5.2.2
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
Set the IICSEL bit in the PMR register to 1 (select I
The following actions must be performed to use the I
Either of the following actions must be performed to use the I
Notes on Clock Synchronous Serial Interface
• Transfer rate
• Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
Sep 26, 2008
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I
223 kbps (= 400/1.18) or more.
Notes on Clock Synchronous Serial I/O with Chip Select
Notes on I
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
before the rising edge of the 8th clock.
operation) to perform 1-byte communications.
Master Receive Mode
Multimaster Operation
2
Page 441 of 453
C bus Interface
2
C bus interface function) to use the I
2
C bus interface in multimaster operation.
2
2
C-bus transfer rate in this MCU should be set to
C bus interface in master receive mode.
2
C bus interface.
21. Usage Notes

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