R5F21275SDFP#U0 Renesas Electronics America, R5F21275SDFP#U0 Datasheet - Page 462

IC R8C/27 MCU FLASH 32LQFP

R5F21275SDFP#U0

Manufacturer Part Number
R5F21275SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21275SDFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
Renesas Electronics America
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Manufacturer:
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
21.7
• Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit
• After changing the A/D operating mode, select an analog input pin again.
• When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The
• When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the
• If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
• Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
CPU clock during A/D conversion.
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.
wait mode) during A/D conversion.
Notes on A/D Converter
Sep 26, 2008
Page 443 of 453
21. Usage Notes

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