R5F21274SNFP#U0 Renesas Electronics America, R5F21274SNFP#U0 Datasheet - Page 138

IC R8C/27 MCU FLASH 32LQFP

R5F21274SNFP#U0

Manufacturer Part Number
R5F21274SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21274SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 12.6
Address Bus
12.1.6.4
CPU Clock
Data Bus
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 12.6 shows the Time Required for Executing Interrupt Sequence.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
NOTES:
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
WR
RD
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
(2) The FLG register is saved to a temporary register
(3) The I, D and U flags in the FLG register are set as follows:
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
Sep 26, 2008
1. This register cannot be used by user.
2. Refer to 12.5 Timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and
00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).
interrupt sequence.
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63
is executed.
I
operations of the timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and the
I
1
2
2
C bus Interface Interrupt.
C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources) for the IR bit
Interrupt Sequence
Time Required for Executing Interrupt Sequence
2
Address
0000h
information
Interrupt
3
Page 119 of 453
4
5
Undefined
Undefined
Undefined
6
7
8
(1)
SP-2 SP-1
is saved to the stack.
9
contents
SP-2
10
contents
SP-1
SP-4
11
contents
(1)
SP-4
12
in the CPU immediately before entering the
SP-3
contents
SP-3
13
VEC
14
contents
VEC
15
VEC+1
contents
VEC+1
16
17
VEC+2
contents
VEC+2
(2)
18
12. Interrupts
19
PC
20

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