R5F21274SNFP#U0 Renesas Electronics America, R5F21274SNFP#U0 Datasheet - Page 274

IC R8C/27 MCU FLASH 32LQFP

R5F21274SNFP#U0

Manufacturer Part Number
R5F21274SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet

Specifications of R5F21274SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 15.11
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TI bit in UiC1
register
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TI bit in UiC1
register
Transfer clock
TE bit in UiC1
register
TXEPT bit in
UiC0 register
IR bit SiTIC
register
Transfer clock
TE bit in UiC1
register
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
TXDi
TXDi
Sep 26, 2008
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Transmit Timing in UART Mode
Write data to UiTB register
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
Transfer from UiTB register to UARTi transmit register
Start
Start
ST
ST
bit
bit
D0
D0
Page 255 of 453
D1
D1
TC
TC
D2
D2
Set to 0 when interrupt request is acknowledged, or set by a program
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7 D8
Parity
bit
P
Stop
Stop
bit
bit
SP
SP SP
Stop
bit
ST
ST
D0
Set to 0 when interrupt request is acknowledged, or set by a program
D1
D0
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
D1
D2
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 1
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 1
D2
D3
D3
D4
D4
D5
D5
D6
Stop pulsing because the TE bit is set to 0
D7
D6
D7
P
D8
SP
SP SP
15. Serial Interface
ST
D0
ST
D1
D0
D1

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