MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part NumberR5F21346CNFP#U0
DescriptionMCU 1KB FLASH 32K ROM 48-LQFP
ManufacturerRenesas Electronics America
SeriesR8C/3x/34C
R5F21346CNFP#U0 datasheet
 


Specifications of R5F21346CNFP#U0

Core ProcessorR8CCore Size16/32-Bit
Speed20MHzConnectivityI²C, LIN, SIO, SSU, UART/USART
PeripheralsPOR, PWM, Voltage Detect, WDTNumber Of I /o43
Program Memory Size32KB (32K x 8)Program Memory TypeFLASH
Ram Size2.5K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 5.5 V
Data ConvertersA/D 12x10b; D/A 2x8bOscillator TypeInternal
Operating Temperature-20°C ~ 85°CPackage / Case48-LQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Old Company Name in Catalogs and Other Documents
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website:
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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April 1
, 2010
Renesas Electronics Corporation

R5F21346CNFP#U0 Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    R8C/34C Group 16 Hardware Manual RENESAS MCU R8C FAMILY / R8C/3x SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas ...

  • Page 4

    This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

  • Page 5

    General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

  • Page 6

    How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...

  • Page 7

    Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...

  • Page 8

    Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) Address XXXXh Bit b7 b6 Symbol XXX7 XXX6 After Reset 0 0 Bit Symbol b0 XXX0 XXX bit b1 XXX1 b2 — ...

  • Page 9

    List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. Asynchronous Communication Interface ...

  • Page 10

    SFR Page Reference ........................................................................................................................... Overview ......................................................................................................................................... 1 1.1 Features ..................................................................................................................................................... 1 1.1.1 Applications .......................................................................................................................................... 1 1.1.2 Specifications ........................................................................................................................................ 2 1.2 Product List ............................................................................................................................................... 4 1.3 Block Diagram .......................................................................................................................................... 5 1.4 Pin Assignment .......................................................................................................................................... 6 1.5 Pin ...

  • Page 11

    Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 37 5.8 Reset Source Determination Function ..................................................................................................... 37 6. Voltage Detection Circuit .............................................................................................................. 38 6.1 Overview ................................................................................................................................................. 38 6.2 Registers .................................................................................................................................................. 42 6.2.1 Voltage Monitor Circuit Control Register (CMPA) ........................................................................... 42 6.2.2 Voltage ...

  • Page 12

    Drive Capacity Control Register 1 (DRR1) ........................................................................................ 88 7.4.23 Input Threshold Control Register 0 (VLT0) ....................................................................................... 89 7.4.24 Input Threshold Control Register 1 (VLT1) ....................................................................................... 90 7.5 Port Settings ............................................................................................................................................ 91 7.6 Unassigned Pin Handling ...................................................................................................................... 111 8. Bus ...

  • Page 13

    Stop Mode ......................................................................................................................................... 146 9.9.2 Wait Mode ........................................................................................................................................ 146 9.9.3 Oscillation Stop Detection Function ................................................................................................. 147 9.9.4 Oscillation Circuit Constants ............................................................................................................ 147 10. Protection .................................................................................................................................... 148 10.1 Register .................................................................................................................................................. 148 10.1.1 Protect Register (PRCR) ................................................................................................................... 148 11. Interrupts ..................................................................................................................................... ...

  • Page 14

    Notes on Interrupts ................................................................................................................................ 174 11.8.1 Reading Address 00000h .................................................................................................................. 174 11.8.2 SP Setting .......................................................................................................................................... 174 11.8.3 External Interrupt and Key Input Interrupt ....................................................................................... 174 11.8.4 Changing Interrupt Sources .............................................................................................................. 175 11.8.5 Rewriting Interrupt Control Register ................................................................................................ 176 12. ...

  • Page 15

    Function Description ............................................................................................................................. 200 15.3.1 Overview ........................................................................................................................................... 200 15.3.2 Activation Sources ............................................................................................................................ 200 15.3.3 Control Data Allocation and DTC Vector Table .............................................................................. 202 15.3.4 Normal Mode .................................................................................................................................... 207 15.3.5 Repeat Mode ..................................................................................................................................... 208 15.3.6 Chain Transfers ................................................................................................................................. 209 15.3.7 ...

  • Page 16

    Timer RB Mode Register (TRBMR) ................................................................................................ 236 18.2.5 Timer RB Prescaler Register (TRBPRE) .......................................................................................... 237 18.2.6 Timer RB Secondary Register (TRBSC) .......................................................................................... 237 18.2.7 Timer RB Primary Register (TRBPR) .............................................................................................. 238 18.2.8 Timer RB/RC Pin Select Register (TRBRCSR) ............................................................................... ...

  • Page 17

    Timer RC I/O Control Register 0 (TRCIOR0) for Input Capture Function ..................................... 275 19.4.2 Timer RC I/O Control Register 1 (TRCIOR1) for Input Capture Function ..................................... 276 19.4.3 Operating Example ........................................................................................................................... 277 19.5 Timer Mode (Output Compare Function) ............................................................................................. ...

  • Page 18

    Timer RD Interrupt Enable Register i (TRDIERi Input Capture Function ............... 322 20.3.13 Timer RD Counter i (TRDi Input Capture Function ................................................. 322 20.3.14 Timer RD General ...

  • Page 19

    Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi PWM Mode ................................................................................................................ 357 20.5.17 Timer RD Pin Select Register 0 (TRDPSR0) ................................................................................... 358 20.5.18 Timer RD Pin Select Register ...

  • Page 20

    Timer RD Trigger Control Register (TRDADCR) ........................................................................... 396 20.8.4 Timer RD Start Register (TRDSTR) in PWM3 Mode ..................................................................... 397 20.8.5 Timer RD Mode Register (TRDMR) in PWM3 Mode ..................................................................... 397 20.8.6 Timer RD Function Control Register (TRDFCR) in PWM3 ...

  • Page 21

    Notes on Timer RE ................................................................................................................................ 431 21.4.1 Starting and Stopping Count ............................................................................................................. 431 21.4.2 Register Setting ................................................................................................................................. 431 21.4.3 Time Reading Procedure of Real-Time Clock Mode ....................................................................... 433 22. Serial Interface (UARTi ( 1)) ............................................................................................ 434 ...

  • Page 22

    CTS/RTS Function ........................................................................................................................... 473 23.4 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 474 23.4.1 Bit Rate ............................................................................................................................................. 478 23.4.2 Measure for Dealing with Communication Errors ........................................................................... 479 23.4.3 LSB First/MSB First Select Function ............................................................................................... 479 23.4.4 Serial Data Logic ...

  • Page 23

    Data Transmission ............................................................................................................................ 518 25.4.3 Data Reception .................................................................................................................................. 520 25.5 Operation in 4-Wire Bus Communication Mode .................................................................................. 524 25.5.1 Initialization in 4-Wire Bus Communication Mode ......................................................................... 525 25.5.2 Data Transmission ............................................................................................................................ 526 25.5.3 Data Reception .................................................................................................................................. 528 25.5.4 SCS ...

  • Page 24

    LIN Status Register (LINST) ............................................................................................................ 572 27.4 Function Description ............................................................................................................................. 573 27.4.1 Master Mode ..................................................................................................................................... 573 27.4.2 Slave Mode ....................................................................................................................................... 576 27.4.3 Bus Collision Detection Function ..................................................................................................... 580 27.4.4 Hardware LIN End Processing ......................................................................................................... 581 27.5 Interrupt Requests .................................................................................................................................. ...

  • Page 25

    Flash Memory ............................................................................................................................. 618 31.1 Overview ............................................................................................................................................... 618 31.2 Memory Map ......................................................................................................................................... 619 31.3 Functions to Prevent Flash Memory from being Rewritten .................................................................. 620 31.3.1 ID Code Check Function .................................................................................................................. 620 31.3.2 ROM Code Protect Function ............................................................................................................ 621 31.3.3 ...

  • Page 26

    Oscillation Circuit Constants ............................................................................................................ 689 34.2 Notes on Interrupts ................................................................................................................................ 690 34.2.1 Reading Address 00000h .................................................................................................................. 690 34.2.2 SP Setting .......................................................................................................................................... 690 34.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 690 34.2.4 Changing Interrupt Sources .............................................................................................................. 691 34.2.5 Rewriting ...

  • Page 27

    Notes bus Interface .................................................................................................................... 711 34.15 Notes on Hardware LIN ........................................................................................................................ 711 34.16 Notes on A/D Converter ........................................................................................................................ 711 34.17 Notes on Flash Memory ........................................................................................................................ 712 34.17.1 CPU Rewrite Mode ........................................................................................................................... 712 34.18 Notes on ...

  • Page 28

    SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Module Standby Control Register 0009h System Clock Control ...

  • Page 29

    Address Register 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC Activation Enable Register 3 008Ch DTC ...

  • Page 30

    Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register ...

  • Page 31

    Address Register 0160h UART1 Transmit/Receive Mode Register 0161h UART1 Bit Rate Register 0162h UART1 Transmit Buffer Register 0163h 0164h UART1 Transmit/Receive Control Register 0 0165h UART1 Transmit/Receive Control Register 1 0166h UART1 Receive Buffer Register 0167h 0168h 0169h 016Ah 016Bh ...

  • Page 32

    Address Register 01E0h Pull-Up Control Register 0 01E1h Pull-Up Control Register 1 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Port P1 Drive Capacity Control Register 01F1h Port P2 Drive Capacity Control Register ...

  • Page 33

    Address Register 2C90h DTC Control Data 10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTC Control Data 11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTC Control Data 12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTC ...

  • Page 34

    R8C/34C Group RENESAS MCU 1. Overview 1.1 Features The R8C/34C Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing ...

  • Page 35

    R8C/34C Group 1.1.2 Specifications Tables 1.1 and 1.2 outline the Specifications for R8C/34C Group. Table 1.1 Specifications for R8C/34C Group (1) Item Function CPU Central processing unit Memory ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O ...

  • Page 36

    R8C/34C Group Table 1.2 Specifications for R8C/34C Group (2) Item Function Serial UART0, UART1 Interface UART2 Synchronous Serial Communication Unit (SSU bus LIN Module A/D Converter D/A Converter Comparator B Flash Memory Operating Frequency/Supply Voltage Current consumption ...

  • Page 37

    R8C/34C Group 1.2 Product List Table 1.3 lists Product List for R8C/34C Group, and Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/34C Group. Table 1.3 Product List for R8C/34C Group Part No. Program ROM R5F21344CNFP 16 ...

  • Page 38

    R8C/34C Group 1.3 Block Diagram Figure 1.2 shows a Block Diagram. I/O ports Port P0 Peripheral functions Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits ...

  • Page 39

    R8C/34C Group 1.4 Pin Assignment Figure 1.3 shows the Pin Assignment (Top View). Tables 1.4 and 1.5 outline the Pin Name Information by Pin Number. P0_7/AN0/DA1(/TRCIOC) P0_6/AN1/DA0(/TRCIOD) P0_5/AN2(/TRCIOB) P0_4/AN3/TREO(/TRCIOB) P0_3/AN4(/CLK1/TRCIOB) P0_2/AN5(/RXD1/TRCIOA/TRCTRG) P0_1/AN6(/TXD1/TRCIOA/TRCTRG) P0_0/AN7(/TRCIOA/TRCTRG) P6_4(/RXD1) P6_3(/TXD1) P6_2(/CLK1) P6_1 Notes: 1. Can ...

  • Page 40

    R8C/34C Group Table 1.4 Pin Name Information by Pin Number (1) Pin Control Pin Port Number 1 P6_0 2 P3_0 3 P4_2 4 MODE 5 (XCIN) P4_3 6 (XCOUT) P4_4 7 RESET 8 XOUT P4_7 9 VSS/AVSS 10 XIN P4_6 ...

  • Page 41

    R8C/34C Group Table 1.5 Pin Name Information by Pin Number (2) Pin Control Pin Port Number 36 P1_0 37 P0_7 38 P0_6 39 P0_5 40 P0_4 41 P0_3 42 P0_2 43 P0_1 44 P0_0 45 P6_4 46 P6_3 47 P6_2 ...

  • Page 42

    R8C/34C Group 1.5 Pin Functions Tables 1.6 and 1.7 list Pin Functions. Table 1.6 Pin Functions (1) Item Pin Name Power supply input VCC, VSS Analog power AVCC, AVSS supply input Reset input RESET MODE MODE XIN clock input XIN ...

  • Page 43

    R8C/34C Group Table 1.7 Pin Functions (2) Item Pin Name Reference voltage VREF input A/D converter AN0 to AN11 ADTRG D/A converter DA0, DA1 Comparator B IVCMP1, IVCMP3 IVREF1, IVREF3 I/O port P0_0 to P0_7, P1_0 to P1_7, P2_0 to ...

  • Page 44

    R8C/34C Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 R2 R3 ...

  • Page 45

    R8C/34C Group 2.1 Data Registers (R0, R1, R2, and R3 16-bit register for transfer, arithmetic, and logic operations. The same applies R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) ...

  • Page 46

    R8C/34C Group 2.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set ...

  • Page 47

    R8C/34C Group 3. Memory 3.1 R8C/34C Group Figure 3 Memory Map of R8C/34C Group. The R8C/34C Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with ...

  • Page 48

    R8C/34C Group 4. Special Function Registers (SFRs) An SFR (special function register control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.13 lists the ID Code Areas and Option Function Select ...

  • Page 49

    R8C/34C Group Table 4.2 SFR Information (2) Address 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h 0044h 0045h 0046h INT4 Interrupt Control Register 0047h Timer RC ...

  • Page 50

    R8C/34C Group Table 4.3 SFR Information (3) Address 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC ...

  • Page 51

    R8C/34C Group Table 4.4 SFR Information (4) Address 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D ...

  • Page 52

    R8C/34C Group Table 4.5 SFR Information (5) Address 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN ...

  • Page 53

    R8C/34C Group Table 4.6 SFR Information (6) Address 0140h Timer RD Control Register 0 0141h Timer RD I/O Control Register A0 0142h Timer RD I/O Control Register C0 0143h Timer RD Status Register 0 0144h Timer RD Interrupt Enable Register ...

  • Page 54

    R8C/34C Group Table 4.7 SFR Information (7) Address 0180h Timer RA Pin Select Register 0181h Timer RB/RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h Timer RD Pin Select Register ...

  • Page 55

    R8C/34C Group Table 4.8 SFR Information (8) Address 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 01C8h 01C9h ...

  • Page 56

    R8C/34C Group Table 4.9 SFR Information (9) Address 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC ...

  • Page 57

    R8C/34C Group Table 4.10 SFR Information (10) Address 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 2C81h 2C82h 2C83h ...

  • Page 58

    R8C/34C Group Table 4.11 SFR Information (11) Address 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h ...

  • Page 59

    R8C/34C Group Table 4.12 SFR Information (12) Address 2CF0h DTC Control Data 22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTC Control Data 23 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h : 2FFFh X: Undefined Note: 1. The ...

  • Page 60

    R8C/34C Group 5. Resets The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows a Block Diagram of Reset Circuit. ...

  • Page 61

    R8C/34C Group Table 5.2 lists the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence. Table 5.2 Pin Functions while RESET Pin Level is “L” Pin ...

  • Page 62

    R8C/34C Group 5.1 Registers 5.1.1 Processor Mode Register 0 (PM0) Address 0004h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Reserved bits b1 — b2 — b3 PM03 Software reset bit b4 — Nothing ...

  • Page 63

    R8C/34C Group 5.1.3 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS After Reset Bit Symbol b0 WDTON Watchdog timer start select bit b1 — Reserved bit b2 ROMCR ROM code protect disable bit b3 ROMCP1 ROM ...

  • Page 64

    R8C/34C Group 5.1.4 Option Function Select Register 2 (OFS2) Address 0FFDBh Bit b7 Symbol — After Reset Bit Symbol b0 WDTUFS0 Watchdog timer underflow period set bit b1 WDTUFS1 b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 WDTRCS1 ...

  • Page 65

    R8C/34C Group 5.2 Hardware Reset A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer ...

  • Page 66

    R8C/34C Group VCC RESET Figure 5.4 Example of Hardware Reset Circuit and Operation RESET Figure 5.5 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation REJ09B0586-0100 Rev.1.00 Jan 13, 2010 Page 33 of 723 ...

  • Page 67

    R8C/34C Group 5.3 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the power-on reset function is enabled and the MCU resets its pins, CPU, ...

  • Page 68

    R8C/34C Group 5.4 Voltage Monitor 0 Reset A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. To use voltage ...

  • Page 69

    R8C/34C Group 5.5 Watchdog Timer Reset When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning ...

  • Page 70

    R8C/34C Group 5.7 Cold Start-Up/Warm Start-Up Determination Function The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during ...

  • Page 71

    R8C/34C Group 6. Voltage Detection Circuit The voltage detection circuit monitors the voltage input to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. 6.1 Overview The detection voltage of voltage detection ...

  • Page 72

    R8C/34C Group VCC Level Selection Circuit (4 levels) VDSEL1 to VDSEL0 Level Selection Circuit (16 levels) VD1S3 to VD1S0 Figure 6.1 Voltage Detection Circuit Block Diagram REJ09B0586-0100 Rev.1.00 Jan 13, 2010 Page 39 of 723 VCA25 + - ≥ Vdet0 ...

  • Page 73

    R8C/34C Group Voltage detection 0 circuit Level selection VCC VDSEL1 to VDSEL0 VW0C0: Bit in VW0C register VCA25: Bit in VCA2 register VDSEL0, VDSEL1: Bits in OFS register Figure 6.2 Block Diagram of Voltage Monitor 0 Reset Generation Circuit Voltage ...

  • Page 74

    R8C/34C Group Voltage detection 2 circuit fOCO-S VCA27 Level VCA13 VCC change + Voltage - detection 2 signal Internal reference voltage When VCA27 bit is set to 0 (disabled), voltage detection 2 signal is driven high. Watchdog timer block Watchdog ...

  • Page 75

    R8C/34C Group 6.2 Registers 6.2.1 Voltage Monitor Circuit Control Register (CMPA) Address 0030h Bit b7 b6 Symbol COMPSEL — After Reset 0 Bit Symbol b0 — Reserved bits b1 — b2 — b3 — b4 IRQ1SEL Voltage monitor 1 interrupt ...

  • Page 76

    R8C/34C Group 6.2.2 Voltage Monitor Circuit Edge Select Register (VCAC) Address 0031h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. ...

  • Page 77

    R8C/34C Group 6.2.4 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset 0 0 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 0 0 The ...

  • Page 78

    R8C/34C Group 6.2.5 Voltage Detection 1 Level Select Register (VD1LS) Address 0036h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 VD1S0 Voltage detection 1 level select bit (Reference voltage when the voltage falls) b1 VD1S1 ...

  • Page 79

    R8C/34C Group 6.2.6 Voltage Monitor 0 Circuit Control Register (VW0C) Address 0038h Bit b7 b6 Symbol — — After Reset 1 1 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 1 ...

  • Page 80

    R8C/34C Group 6.2.7 Voltage Monitor 1 Circuit Control Register (VW1C) Address 0039h Bit b7 b6 Symbol VW1C7 — After Reset 1 0 Bit Symbol b0 VW1C0 Voltage monitor 1 interrupt enable bit b1 VW1C1 Voltage monitor 1 digital filter disable ...

  • Page 81

    R8C/34C Group 6.2.8 Voltage Monitor 2 Circuit Control Register (VW2C) Address 003Ah Bit b7 b6 Symbol VW2C7 — After Reset 1 0 Bit Symbol b0 VW2C0 Voltage monitor 2 interrupt enable bit b1 VW2C1 Voltage monitor 2 digital filter disable ...

  • Page 82

    R8C/34C Group 6.2.9 Option Function Select Register (OFS) Address 0FFFFh Bit b7 Symbol CSPROINI LVDAS After Reset Bit Symbol b0 WDTON Watchdog timer start select bit b1 — Reserved bit b2 ROMCR ROM code protect disable bit b3 ROMCP1 ROM ...

  • Page 83

    R8C/34C Group 6.3 VCC Input Voltage 6.3.1 Monitoring Vdet0 Vdet0 cannot be monitored. 6.3.2 Monitoring Vdet1 Once the following settings are made, the comparison result of voltage monitor 1 can be monitored by the VW1C3 bit in the VW1C register ...

  • Page 84

    R8C/34C Group 6.4 Voltage Monitor 0 Reset To use voltage monitor 0 reset, set the LVDAS bit in the OFS register to 0 (voltage monitor 0 reset enabled after reset). Figure 6.5 shows an Operating Example of Voltage Monitor 0 ...

  • Page 85

    R8C/34C Group 6.5 Voltage Monitor 1 Interrupt Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an Operating Example of Voltage Monitor 1 Interrupt. To use the voltage monitor 1 interrupt to ...

  • Page 86

    R8C/34C Group Vdet1 1.8 V (1) VW1C3 bit VW1C2 bit VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital ...

  • Page 87

    R8C/34C Group 6.6 Voltage Monitor 2 Interrupt Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an Operating Example of Voltage Monitor 2 Interrupt. To use the voltage monitor 2 interrupt to ...

  • Page 88

    R8C/34C Group Vdet2 (1) 1.8 V VCA13 bit VW2C2 bit VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital ...

  • Page 89

    R8C/34C Group 7. I/O Ports There are 43 I/O ports P0 to P2, P3_0 and P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, P6, and P6 (P4_3 and P4_4 can be used as I/O ports if the XCIN clock oscillation ...

  • Page 90

    R8C/34C Group 7.2 Effect on Peripheral Functions I/O ports function as I/O ports for peripheral functions (refer to Table 1.4 Pin Name Information by Pin Number (1) and Table 1.5 Pin Name Information by Pin Number (2)). Table 7.3 lists ...

  • Page 91

    R8C/34C Group P0_0 to P0_5 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of A/D converter P0_6 and P0_7 Direction register Output from individual peripheral function ...

  • Page 92

    R8C/34C Group P1_0 to P1_3 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Analog input of A/D converter Note: 1. symbolizes a parasitic diode. Ensure the input voltage ...

  • Page 93

    R8C/34C Group P1_4 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function P1_5 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input ...

  • Page 94

    R8C/34C Group P1_6 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of comparator B P1_7 Direction register Output from individual peripheral function enabled Port latch Data ...

  • Page 95

    R8C/34C Group P2_0 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Input to external interrupt P2_1 to P2_7 Direction register Output from individual peripheral function enabled Data bus ...

  • Page 96

    R8C/34C Group P3_0 and P3_1 Direction register Output from individual peripheral function enabled Data bus Port latch Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. IOINSEL: Bit in PINSR register Figure ...

  • Page 97

    R8C/34C Group P3_3 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Analog input of comparator B Input to external interrupt P3_4 Direction register Output from individual peripheral function ...

  • Page 98

    R8C/34C Group P3_5 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. ...

  • Page 99

    R8C/34C Group P3_7 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. ...

  • Page 100

    R8C/34C Group P4_2/VREF Data bus P4_3/XCIN Pull-up selection Direction register Port latch Data bus P4_4/XCOUT Pull-up selection Direction register Data bus Port latch Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. ...

  • Page 101

    R8C/34C Group P4_5 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Input to external interrupt A/D trigger input Note: 1. symbolizes a parasitic diode. Ensure the input voltage ...

  • Page 102

    R8C/34C Group P4_6/XIN Pull-up selection Direction register Data bus Port latch P4_7/XOUT Pull-up selection Direction register Data bus Port latch Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. CM05: Bits in ...

  • Page 103

    R8C/34C Group P6_0 and P6_3 Direction register Output from individual peripheral function enabled Port latch Data bus P6_1 Direction register Data bus Port latch Note: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed ...

  • Page 104

    R8C/34C Group P6_2 Direction register Output from individual peripheral function enabled Port latch Data bus Pin select register Input to individual peripheral function P6_4 Direction register Data bus Port latch Pin select register Input to individual peripheral function Note: 1. ...

  • Page 105

    R8C/34C Group P6_5 to P6_7 Direction register Output from individual peripheral function enabled Data bus Port latch Pin select register Input to individual peripheral function Input to external interrupt Note: 1. symbolizes a parasitic diode. Ensure the input voltage to ...

  • Page 106

    R8C/34C Group 7.4 Registers 7.4.1 Port Pi Direction Register (PDi Address 00E2h (PD0 (1) ), 00E3h (PD1), 00E6h (PD2), 00E7h (PD3 Bit b7 b6 Symbol PDi_7 PDi_6 After Reset 0 0 Bit Symbol ...

  • Page 107

    R8C/34C Group 7.4.2 Port Pi Register (Pi Address 00E0h(P0), 00E1h(P1), 00E4h(P2), 00E5h(P3 Bit b7 b6 Symbol Pi_7 Pi_6 After Reset X X Bit Symbol b0 Pi_0 Port Pi_0 bit b1 Pi_1 Port Pi_1 ...

  • Page 108

    R8C/34C Group 7.4.3 Timer RA Pin Select Register (TRASR) Address 0180h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TRAIOSEL0 TRAIO pin select bit b1 TRAIOSEL1 b2 — Reserved bit b3 TRAOSEL0 TRAO pin select ...

  • Page 109

    R8C/34C Group 7.4.5 Timer RC Pin Select Register 0 (TRCPSR0) Address 0182h Bit b7 b6 Symbol — TRCIOBSEL2 TRCIOBSEL1 TRCIOBSEL0 After Reset 0 0 Bit Symbol b0 TRCIOASEL0 TRCIOA/TRCTRG pin select bit b1 TRCIOASEL1 b2 TRCIOASEL2 b3 — Nothing is ...

  • Page 110

    R8C/34C Group 7.4.6 Timer RC Pin Select Register 1 (TRCPSR1) Address 0183h Bit b7 b6 Symbol — TRCIODSEL2 TRCIODSEL1 TRCIODSEL0 After Reset 0 0 Bit Symbol b0 TRCIOCSEL0 TRCIOC pin select bit b1 TRCIOCSEL1 b2 TRCIOCSEL2 b3 — Nothing is ...

  • Page 111

    R8C/34C Group 7.4.7 Timer RD Pin Select Register 0 (TRDPSR0) Address 0184h Bit b7 b6 Symbol — TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 TRDIOB0SEL1 TRDIOB0SEL0 After Reset 0 0 Bit Symbol b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 — Nothing is assigned. If ...

  • Page 112

    R8C/34C Group 7.4.9 Timer Pin Select Register (TIMSR) Address 0186h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TREOSEL0 TREO pin select bit b1 — Nothing is assigned. If necessary, set to 0. When read, ...

  • Page 113

    R8C/34C Group 7.4.10 UART0 Pin Select Register (U0SR) Address 0188h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD0SEL0 TXD0 pin select bit b1 — Nothing is assigned. If necessary, set to 0. When read, ...

  • Page 114

    R8C/34C Group 7.4.12 UART2 Pin Select Register 0 (U2SR0) Address 018Ah Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 TXD2SEL0 TXD2/SDA2 pin select bit b1 TXD2SEL1 b2 TXD2SEL2 b3 — Nothing is assigned. If necessary, ...

  • Page 115

    R8C/34C Group 7.4.14 SSU/IIC Pin Select Register (SSUIICSR) Address 018Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 IICSEL 2 SSU/I C bus switch bit b1 — Reserved bit b2 — Nothing is assigned. If ...

  • Page 116

    R8C/34C Group 7.4.15 INT Interrupt Input Pin Select Register (INTSR) Address 018Eh Bit b7 b6 Symbol INT3SEL1 INT3SEL0 After Reset 0 0 Bit Symbol b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. ...

  • Page 117

    R8C/34C Group 7.4.16 I/O Function Pin Select Register (PINSR) Address 018Fh Bit b7 b6 Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL After Reset 0 0 Bit Symbol b0 XCSEL XCIN/XCOUT pin connect bit b1 — Reserved bit b2 — Nothing is ...

  • Page 118

    R8C/34C Group 7.4.17 Pull-Up Control Register 0 (PUR0) Address 01E0h Bit b7 b6 Symbol PU07 PU06 After Reset 0 0 Bit Symbol b0 PU00 P0_0 to P0_3 pull-up b1 PU01 P0_4 to P0_7 pull-up b2 PU02 P1_0 to P1_3 pull-up ...

  • Page 119

    R8C/34C Group 7.4.19 Port P1 Drive Capacity Control Register (P1DRR) Address 01F0h Bit b7 b6 Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0 After Reset 0 0 Bit Symbol b0 P1DRR0 P1_0 drive capacity b1 P1DRR1 P1_1 drive capacity ...

  • Page 120

    R8C/34C Group 7.4.21 Drive Capacity Control Register 0 (DRR0) Address 01F2h Bit b7 b6 Symbol DRR07 DRR06 After Reset 0 0 Bit Symbol b0 DRR00 P0_0 to P0_3 drive capacity b1 DRR01 P0_4 to P0_7 drive capacity b2 — Nothing ...

  • Page 121

    R8C/34C Group 7.4.22 Drive Capacity Control Register 1 (DRR1) Address 01F3h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 DRR10 P4_3 drive capacity b1 DRR11 P4_4 to P4_7 drive capacity b2 — Nothing is assigned. ...

  • Page 122

    R8C/34C Group 7.4.23 Input Threshold Control Register 0 (VLT0) Address 01F5h Bit b7 b6 Symbol VLT07 VLT06 After Reset 0 0 Bit Symbol b0 VLT00 P0 input level select bit b1 VLT01 b2 VLT02 P1 input level select bit b3 ...

  • Page 123

    R8C/34C Group 7.4.24 Input Threshold Control Register 1 (VLT1) Address 01F6h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 VLT10 P4_2 to P4_7 input level select bit b1 VLT11 b2 — Reserved bits b3 — ...

  • Page 124

    R8C/34C Group 7.5 Port Settings Tables 7.5 to 7.61 list the port settings. Table 7.5 Port P0_0/AN7/TRCIOA/TRCTRG Register PD0 ADINSEL CH Bit PD0_0 Setting Value ...

  • Page 125

    R8C/34C Group Table 7.8 Port P0_3/AN4/CLK1/TRCIOB Register PD0 ADINSEL CH ADGSEL CLK1SEL SMD Bit PD0_3 Setting ...

  • Page 126

    R8C/34C Group Table 7.11 Port P0_6/AN1/DA0/TRCIOD Register PD0 ADINSEL CH Bit PD0_6 Setting Value ...

  • Page 127

    R8C/34C Group Table 7.14 Port P1_1/KI1/AN9/TRCIOA/TRCTRG Register PD1 KIEN Bit PD1_1 KI1EN Setting Value Notes: 1. Pulled ...

  • Page 128

    R8C/34C Group Table 7.16 Port P1_3/KI3/AN11/TRCIOC Register PD1 KIEN CH Bit PD1_3 KI3EN Setting Value ...

  • Page 129

    R8C/34C Group Table 7.18 Port P1_5/RXD0/TRAIO/INT1 Register PD1 U0SR Bit PD1_5 RXD0SEL0 0 X Other than 10b 1 X Other than 10b 0 1 Other than 10b Other than 10b 0 X Setting Value X X ...

  • Page 130

    R8C/34C Group Table 7.21 Port P2_0/TRDIOA0/TRDCLK/INT1/TRCIOB Register PD2 TRDPSR0 Bit PD2_0 TRDIOA0SEL0 Setting X 1 Value Notes: 1. Pulled up by setting the PU04 ...

  • Page 131

    R8C/34C Group Table 7.23 Port P2_2/TRDIOB0/TRCIOD Register PD2 TRDPSR0 TRDIOB0SEL Bit PD2_2 1 0 Other than 10b 1 Other than 10b 0 1 Setting X 1 Value Notes: 1. Pulled up by ...

  • Page 132

    R8C/34C Group Table 7.27 Port P2_6/TRDIOC1 Register PD2 TRDPSR1 Bit PD2_6 TRDIOC1SEL0 0 1 Setting Value Notes: 1. Pulled up by setting the PU05 bit in the PUR0 register Output drive ...

  • Page 133

    R8C/34C Group Table 7.31 Port P3_3/INT3/TRCCLK/SCS/CTS2/RTS2/IVCMP3 Register PD3 SSMR2 INTSR CSS INT3SEL Bit PD3_3 ...

  • Page 134

    R8C/34C Group Table 7.33 Port P3_5/SCL/SSCK/TRCIOD/CLK2 Register PD3 SSUIICSR ICCR1 Bit PD3_5 IICSEL ICE Setting 0 Value 1 0 ...

  • Page 135

    R8C/34C Group Table 7.34 Port P3_7/SSO/TXD2/SDA2/RXD2/SCL2/TRAO/SDA Register PD3 SSUIICSR ICCR1 Bit PD3_7 IICSEL ICE Setting Value ...

  • Page 136

    R8C/34C Group Table 7.35 Port P4_2/VREF Register ADCON1 Bit ADSTBY 0 Setting Value Other than 000b Table 7.36 Port P4_3/XCIN Register PD4 PINSR CM0 Bit PD4_3 XCSEL CM03 CM04 CM10 CM12 ...

  • Page 137

    R8C/34C Group Table 7.38 Port P4_5/INT0/RXD2/SCL2/ADTRG Register PD4 INTEN Bit PD4_5 INT0EN Setting Value Notes: 1. Pulled up by setting the PU11 bit in ...

  • Page 138

    R8C/34C Group Table 7.41 Port P6_0/TREO Register PD6 Bit PD6_0 TREOSEL0 0 Setting 1 Value Notes: 1. Pulled up by setting the PU14 bit in the PUR1 register Output drive capacity high ...

  • Page 139

    R8C/34C Group Table 7.45 Port P6_4/RXD1 Register PD6 Bit PD6_4 RXD1SEL1 0 Setting 1 Value Notes: 1. Pulled up by setting the PU15 bit in the PUR1 register Output drive capacity high ...

  • Page 140

    R8C/34C Group Table 7.47 Port P6_6/INT2/TXD2/SDA2/TRCIOC Register PD6 INTEN U2SR0 TXD2SEL Bit PD6_6 INT2EN 2 Other than 0 X 101b Other than 1 X 101b Other than 0 1 101b Setting Value Other than ...

  • Page 141

    R8C/34C Group Table 7.49 TRBO Pin Setting Register TRBIOC Bit TOCNT TMOD1 0 1 Setting Value 0 0 Table 7.50 TRCIOA Pin Setting Register TRCOER TRCMR Bit EA PWM2 Setting 1 Value ...

  • Page 142

    R8C/34C Group Table 7.54 TRDIOA0 Pin Setting Register TRDOER1 Bit EA0 CMD1 Setting 0 0 Value Table 7.55 TRDIOB0 Pin Setting Register TRDOER1 TRDFCR Bit EB0 CMD1 CMD0 PWM3 X ...

  • Page 143

    R8C/34C Group Table 7.58 TRDIOA1 Pin Setting Register TRDOER1 TRDFCR Bit EA1 CMD1 CMD0 PWM3 Setting Value Table 7.59 TRDIOB1 Pin Setting Register TRDOER1 TRDFCR Bit EB1 CMD1 ...

  • Page 144

    R8C/34C Group 7.6 Unassigned Pin Handling Table 7.62 lists Unassigned Pin Handling. Table 7.62 Unassigned Pin Handling Pin Name Ports P0 to P2, P3_0 and P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_7, P6 Port P4_2/VREF (3) RESET Notes: 1. ...

  • Page 145

    R8C/34C Group 8. Bus The bus cycles differ when accessing ROM, RAM, DTC vector area, DTC control data and when accessing SFR. Table 8.1 lists Bus Cycles by Access Area of R8C/34C Group. ROM, RAM, DTC vector area, DTC control ...

  • Page 146

    R8C/34C Group However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD Timer RD: Registers TRDi ( 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi ...

  • Page 147

    R8C/34C Group 9. Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit: • XIN clock oscillation circuit • XCIN clock oscillation circuit • Low-speed on-chip oscillator • High-speed on-chip oscillator • Low-speed on-chip oscillator for ...

  • Page 148

    R8C/34C Group CM04 XCIN XCOUT CM04 CM03 S Q CM10 = 1 (stop mode) RESET R Power-on reset Software reset Voltage monitor 0 reset S Q Interrupt request WAIT instruction R CM30 CM13 XIN XOUT CM13 CM05 CM02, CM03, CM04, ...

  • Page 149

    R8C/34C Group fC fC2 fC4 fC32 fOCO40M fOCO128 fOCO fOCO-F fOCO-WDT Timer RA Timer RB INT0 f32 CPU clock Figure 9.2 Peripheral Function Clock REJ09B0586-0100 Rev.1.00 Jan 13, 2010 Page 116 of 723 Watchdog timer Timer ...

  • Page 150

    R8C/34C Group 9.2 Registers 9.2.1 System Clock Control Register 0 (CM0) Address 0006h Bit b7 b6 Symbol CM07 CM06 After Reset 0 0 Bit Symbol Bit Name b0 — Reserved bits b1 — b2 CM02 Wait mode peripheral function clock ...

  • Page 151

    R8C/34C Group 9.2.2 System Clock Control Register 1 (CM1) Address 0007h Bit b7 b6 Symbol CM17 CM16 After Reset 0 0 Bit Symbol b0 CM10 All clock stop control bit b1 CM11 XIN-XOUT on-chip feedback resistor select bit b2 CM12 ...

  • Page 152

    R8C/34C Group 9.2.3 System Clock Control Register 3 (CM3) Address 0009h Bit b7 b6 Symbol CM37 CM36 After Reset 0 0 Bit Symbol b0 CM30 Wait control bit b1 — Nothing is assigned. If necessary, set to 0. When read, ...

  • Page 153

    R8C/34C Group CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). Since the XIN clock, XCIN clock, and the on-chip oscillator clock do not stop, the ...

  • Page 154

    R8C/34C Group 9.2.4 Oscillation Stop Detection Register (OCD) Address 000Ch Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 OCD0 Oscillation stop detection enable bit b1 OCD1 Oscillation stop detection interrupt enable bit b2 OCD2 System ...

  • Page 155

    R8C/34C Group 9.2.6 High-Speed On-Chip Oscillator Control Register 0 (FRA0) Address 0023h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA00 High-speed on-chip oscillator enable bit b1 FRA01 High-speed on-chip oscillator select bit b2 — ...

  • Page 156

    R8C/34C Group 9.2.8 High-Speed On-Chip Oscillator Control Register 2 (FRA2) Address 0025h Bit b7 b6 Symbol — — After Reset 0 0 Bit Symbol b0 FRA20 High-speed on-chip oscillator frequency switching bit b1 FRA21 b2 FRA22 b3 — Reserved bits ...

  • Page 157

    R8C/34C Group 9.2.10 High-Speed On-Chip Oscillator Control Register 4 (FRA4) Address 0029h Bit b7 b6 Symbol — — After Reset Bit b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the ...

  • Page 158

    R8C/34C Group 9.2.14 Voltage Detect Register 2 (VCA2) Address 0034h Bit b7 b6 Symbol VCA27 VCA26 After Reset 0 0 The above applies when the LVDAS bit in the OFS register is set to 1. After Reset 0 0 The ...

  • Page 159

    R8C/34C Group 9.2.15 I/O Function Pin Select Register (PINSR) Address 018Fh Bit b7 b6 Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL After Reset 0 0 Bit Symbol b0 XCSEL XCIN/XCOUT pin connect bit b1 — Reserved bit b2 — Nothing is ...

  • Page 160

    R8C/34C Group Procedure for enabling reduced internal power consumption using VCA20 bit Enter low-speed clock mode or Step (1) low-speed on-chip oscillator mode Stop XIN clock and Step (2) high-speed on-chip oscillator clock VCA20 ← 1 Step (3) (internal power ...

  • Page 161

    R8C/34C Group The clocks generated by the clock generation circuits are described below. 9.3 XIN Clock The XIN clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral ...

  • Page 162

    R8C/34C Group 9.4 On-Chip Oscillator Clock The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed on- chip oscillator). This clock is selected by the FRA01 bit in the FRA0 register. 9.4.1 Low-Speed On-Chip Oscillator ...

  • Page 163

    R8C/34C Group 9.5 XCIN Clock The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XCIN clock oscillation circuit is configured by connecting ...

  • Page 164

    R8C/34C Group 9.6 CPU Clock and Peripheral Function Clock There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 9.1 Clock Generation Circuit. 9.6.1 System Clock The system ...

  • Page 165

    R8C/34C Group 9.6.7 fOCO-S fOCO operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (low- speed on-chip oscillator on). In wait mode, ...

  • Page 166

    R8C/34C Group 9.7 Power Control There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode. 9.7.1 Standard Operating Mode Standard operating mode is further separated into four modes. ...

  • Page 167

    R8C/34C Group 9.7.1.1 High-Speed Clock Mode The XIN clock divided by 1 (no division used as the CPU clock. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 ...

  • Page 168

    R8C/34C Group 9.7.2 Wait Mode Since the CPU clock stops in wait mode, the CPU operating with the CPU clock and the watchdog timer when count source protection mode is disabled stop. Since the XIN clock, XCIN clock, and on-chip ...

  • Page 169

    R8C/34C Group 9.7.2.4 Exiting Wait Mode The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does ...

  • Page 170

    R8C/34C Group Figure 9.6 shows the Time from Wait Mode to First Instruction Execution following Exit after CM30 Bit in CM3 Register is Set to 1 (MCU Enters Wait Mode). To use a peripheral function interrupt to exit wait mode, ...

  • Page 171

    R8C/34C Group Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed. To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set ...

  • Page 172

    R8C/34C Group 9.7.3 Stop Mode Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral function clocks stop and the CPU and the peripheral functions operating with these clocks also stop. The least power required to ...

  • Page 173

    R8C/34C Group 9.7.3.3 Exiting Stop Mode The MCU exits stop mode by a reset or peripheral function interrupt. Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit stop mode, ...

  • Page 174

    R8C/34C Group Figure 9.9 shows the State Transitions in Power Control Mode. State Transitions in Power Control Mode Standard operating mode CM14 = 0 OCD2 = 1 FRA01 = 0 High-speed clock mode CM05 = 0 CM07 = 0 CM13 ...

  • Page 175

    R8C/34C Group 9.8 Oscillation Stop Detection Function The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table ...

  • Page 176

    R8C/34C Group 9.8.1 How to Use Oscillation Stop Detection Function • The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. To use the oscillation stop ...

  • Page 177

    R8C/34C Group Table 9.7 Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Generated Interrupt Source Oscillation stop detection ((a) or (b)) Watchdog timer Voltage monitor 1 Voltage monitor 2 NO ...

  • Page 178

    R8C/34C Group Determination of Interrupt sources NO OCD3 = 1? (XIN clock stops) YES (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock)? Set OCD1 bit to 0 (oscillation stop detection (1) interrupt ...

  • Page 179

    R8C/34C Group 9.9 Notes on Clock Generation Circuit 9.9.1 Stop Mode To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 ...

  • Page 180

    R8C/34C Group 9.9.3 Oscillation Stop Detection Function Since the oscillation stop detection function cannot be used if the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b. 9.9.4 Oscillation Circuit Constants Consult the oscillator manufacturer ...

  • Page 181

    R8C/34C Group 10. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the PRCR register are as follows: • Registers protected by PRC0 bit: Registers CM0, CM1, ...

  • Page 182

    R8C/34C Group 11. Interrupts 11.1 Overview 11.1.1 Types of Interrupts Figure 11.1 shows the Types of Interrupts. Software (non-maskable interrupts) Interrupts Hardware Notes: 1. Peripheral function interrupts are generated by the peripheral functions in the MCU not use ...

  • Page 183

    R8C/34C Group 11.1.2 Software Interrupts A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable. 11.1.2.1 Undefined Instruction Interrupt An undefined instruction interrupt is generated when the UND instruction is executed. 11.1.2.2 Overflow Interrupt An overflow ...

  • Page 184

    R8C/34C Group 11.1.3 Special Interrupts Special interrupts are non-maskable. 11.1.3.1 Watchdog Timer Interrupt A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer. 11.1.3.2 Oscillation Stop Detection Interrupt An oscillation stop detection interrupt ...

  • Page 185

    R8C/34C Group 11.1.5 Interrupts and Interrupt Vectors There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in ...

  • Page 186

    R8C/34C Group 11.1.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 11.2 lists the Relocatable Vector Tables. Table 11.2 Relocatable Vector Tables Interrupt Source ( ...

  • Page 187

    R8C/34C Group 11.2 Registers 11.2.1 Interrupt Control Register (TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC), 0051h (S0TIC), 0052h (S0RIC), 0053h (S1TIC), 0054h ...

  • Page 188

    R8C/34C Group 11.2.2 Interrupt Control Register (FMRDYIC, TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC) Address 0041h (FMRDYIC), 0047h (TRCIC), 0048h (TRD0IC), 0049h (TRD1IC), 004Fh (SSUIC/IICIC Bit b7 b6 Symbol — — After Reset X X Bit Symbol b0 ILVL0 Interrupt priority level select ...

  • Page 189

    R8C/34C Group 11.2.3 INTi Interrupt Control Register (INTiIC Address 0046h (INT4IC), 0055h (INT2IC), 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) Bit b7 b6 Symbol — — After Reset X X Bit Symbol b0 ILVL0 Interrupt priority ...

  • Page 190

    R8C/34C Group 11.3 Interrupt Control The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 ...

  • Page 191

    R8C/34C Group 11.3.4 Interrupt Sequence The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is executed. When an interrupt request is generated while an instruction is being executed, the ...

  • Page 192

    R8C/34C Group 11.3.5 Interrupt Response Time Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt response ...

  • Page 193

    R8C/34C Group 11.3.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the ...

  • Page 194

    R8C/34C Group The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 11.6 shows the Register Saving Operation. Stack Address [SP]−5 PCL [SP]−4 [SP]−3 PCM FLGL ...

  • Page 195

    R8C/34C Group 11.3.8 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved on the stack, are automatically restored. The program, that was running ...

  • Page 196

    R8C/34C Group 11.3.10 Interrupt Priority Level Selection Circuit The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 11.8 shows the Interrupt Priority Level Selection Circuit. Priority level of interrupts Voltage monitor 1 UART2 bus ...

  • Page 197

    R8C/34C Group 11.4 INT Interrupt 11.4.1 INTi Interrupt ( The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN register (enabled). The ...

  • Page 198

    R8C/34C Group 11.4.3 External Input Enable Register 0 (INTEN) Address 01FAh Bit b7 b6 Symbol INT3PL INT3EN After Reset 0 0 Bit Symbol b0 INT0EN INT0 input enable bit b1 INT0PL INT0 input polarity select bit b2 INT1EN INT1 input ...

  • Page 199

    R8C/34C Group 11.4.5 INT Input Filter Select Register 0 (INTF) Address 01FCh Bit b7 b6 Symbol INT3F1 INT3F0 After Reset 0 0 Bit Symbol b0 INT0F0 INT0 input filter select bit b1 INT0F1 b2 INT1F0 INT1 input filter select bit ...

  • Page 200

    R8C/34C Group 11.4.7 INTi Input Filter ( The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 and INTiF0 in registers INTF and INTF1. The INTi level is sampled every sampling ...