R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 125

MCU 1KB FLASH 32K ROM 48-LQFP

R5F21346CNFP#U0

Manufacturer Part Number
R5F21346CNFP#U0
Description
MCU 1KB FLASH 32K ROM 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/3x/34Cr
Datasheet

Specifications of R5F21346CNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
43
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F21346CNFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 92 of 723
Table 7.8
X: 0 or 1
Notes:
Table 7.9
X: 0 or 1
Notes:
Table 7.10
X: 0 or 1
Notes:
Register
Register
Register
Setting
Setting
Setting
Value
Value
Value
Bit
Bit
Bit
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the DRR00 bit in the DRR0 register to 1.
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the DRR01 bit in the DRR0 register to 1.
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the DRR01 bit in the DRR0 register to 1.
PD0_3
PD0_4
PD0_5
PD0
PD0
PD0
X
X
0
1
0
0
0
X
X
0
1
0
0
0
1
0
0
X
Port P0_3/AN4/CLK1/TRCIOB
Port P0_4/AN3/TREO/TRCIOB
Port P0_5/AN2/TRCIOB
2 1 0
X X X
X X X
1 0 0
X X X
X X X
X X X
X X X
2 1 0
X X X
X X X
0 1 1
X X X
X X X
X X X
CH
CH
X
X
X
X
2
0
ADINSEL
ADINSEL
CH
ADGSEL CLK1SEL SMD
1
X
X
1
X
X
1
X
X
0
X
X
X
X
ADGSEL
X
X
X
X
X
1
0
ADINSEL
0
X
X
0
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
0
0
than 01b
than 01b
than 01b
than 01b
than 01b
1
0
0
TREOSEL0
ADGSEL
U1SR
X
X
X
X
Other
Other
Other
Other
Other
1
0
TIMSR
Other than 01b
Other than 01b
Other than 01b
X
X
0
0
1
1
X
X
X
X
0
0
2 1 0
X X X
X X X
X X X
X X X
0 0 1
X X X
X X X
Other than 100b
Other than 100b
Other than 100b
TRECR1
2
1
1
TOENA
TRCIOBSEL
U1MR
TRCPSR0
X
X
1
CKDIR
1
0
0
X
X
X
X
X
1
0
TRCIOBSEL
2
0
0
TRCPSR0
Other than
Other than
Other than
Other than
0
0
0
TRCIOBSEL
X
X
2
0
0
TRCPSR0
Other than
Other than
Other than
011b
011b
011b
011b
1
1
1
010b
010b
010b
X
X
1
1
1
TRCIOB Pin Setting
TRCIOB Pin Setting
Refer to Table 7.51
Refer to Table 7.51
0
1
1
Timer RC Setting
X
X
0
0
0
TRCIOB Pin Setting
TRCIOB Pin Setting
Refer to Table 7.51
Refer to Table 7.51
Timer RC Setting
TRCIOB Pin Setting
TRCIOB Pin Setting
X
X
X
Refer to Table 7.51
Refer to Table 7.51
Timer RC Setting
X
X
X
X
X
X
X
X
X
Input port
Output port
A/D converter input (AN2)
TRCIOB input
TRCIOB output
Input port
Output port
A/D converter input (AN3)
TREO output
TRCIOB input
TRCIOB output
Input port
Output port
A/D converter input
(AN4)
CLK1 (external clock)
input
CLK1 (internal clock)
output
TRCIOB input
TRCIOB output
(1)
Function
(2)
Function
(1)
(1)
(1)
(1)
(2)
Function
(2)
(2)
(2)
(1)
(1)
(2)
(2)
7. I/O Ports
(1)
(2)
(1)
(1)

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