R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 138

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 105 of 723
Table 7.41
X: 0 or 1
Notes:
Table 7.42
Notes:
Table 7.43
X: 0 or 1
Notes:
Table 7.44
X: 0 or 1
Notes:
Register
Register
Register
Register
Setting
Setting
Setting
Setting
Value
Value
Value
Value
Bit
Bit
Bit
Bit
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
2. Output drive capacity high by setting the DRR14 bit in the DRR1 register to 1.
3. N-channel open-drain output by setting the NCH bit in the U1C0 register to 1.
PD6_2
PD6_3
PD6
PD6
0
1
0
X
X
PD6_0
PD6_1
0
1
PD6
PD6
Port P6_0/TREO
Port P6_2/CLK1
Port P6_3/TXD1
Port P6_1
X
0
1
0
1
CLK1SEL1 CLK1SEL0
TXD1SEL1
Other than 10b
Other than 10b
1
1
Input port
Output port
1
Other than 10b
Other than 10b
U1SR
TREOSEL0
U1SR
TIMSR
1
TXD1SEL0
(1)
0
0
Other than 11b
Other than 11b
(2)
0
Function
SMD2
X
X
X
0
TRECR1
TOENA
SMD2
1
X
X
0
1
SMD1
X
X
X
0
U1MR
Input port
Output port
TREO output
U1MR
SMD1
X
X
0
1
SMD0
X
X
X
1
(1)
(2)
(2)
SMD0
CKDIR
X
X
1
0
1
0
X
X
Function
1
0
Input port
Output port
CLK1 (external clock) input
CLK1 (internal clock) output
Input port
Output port
TXD1 output
(1)
(1)
(2)
(2)
Function
Function
(2, 3)
7. I/O Ports
(1)
(2)