R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 205

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 172 of 723
11.7
Figure 11.12
Table 11.10
Timer RC
Timer RD
Synchronous serial
communication unit
I
Flash memory
2
The timer RC interrupt, timer RD (timer RD0) interrupt, timer RD (timer RD1) interrupt, synchronous serial
communication unit interrupt, I
request sources. An interrupt request is generated by the logical OR of several interrupt request sources and is
reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these peripheral functions
has its own interrupt request source status register (status register) and interrupt request source enable register
(enable register) to control the generation of interrupt requests (change of the IR bit in the interrupt control
register). Table 11.10 lists the Registers Associated with Timer RC Interrupt, Timer RD Interrupt, Synchronous
Serial Communication Unit Interrupt, I
shows a Block Diagram of Timer RD Interrupt.
C bus interface
Peripheral Function
Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Communication
Unit Interrupt, I
(Interrupts with Multiple Interrupt Request Sources)
Name
Timer RD0
Timer RD1
Registers Associated with Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial
Communication Unit Interrupt, I
Block Diagram of Timer RD Interrupt
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIERi register
OVIE bit
UDF bit
OVF bit
Timer RDi
TRCSR
TRDSR0
TRDSR1
SSSR
ICSR
RDYSTI
BSYAEI
Interrupt Request Source
IMIEA bit
IMIEB bit
IMIEC bit
IMIED bit
2
IMFC bit
IMFD bit
IMFA bit
IMFB bit
2
C bus Interface Interrupt, and Flash Memory Interrupt
C bus interface interrupt, and flash memory interrupt each have multiple interrupt
Status Register of
2
C bus Interface Interrupt, and Flash Memory Interrupt and Figure 11.12
2
C bus Interface Interrupt, and Flash Memory Interrupt
Interrupt Request Source
TRCIER
TRDIER0
TRDIER1
SSER
ICIER
RDYSTIE
BSYAEIE
CMDERIE
Enable Register of
Timer RDi
interrupt request
(IR bit in TRDiIC register)
TRD0IC
TRD1IC
TRCIC
SSUIC
IICIC
FMRDYIC
Interrupt Control
Register
11. Interrupts