R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 241

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 208 of 723
Figure 15.9
15.3.5
Table 15.7
j =0 to 23
DTC block size register j
DTC transfer count register j
DTC transfer count reload register j DTRLDj
DTC source address register j
DTC destination address register j
One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be
specified as the repeat area. The number of transfer times can be 1 to 255. On completion of the specified
number of transfer times, the DTCCTj (i =0 to 23) register and the address specified for the repeat area are
initialized to continue transfers. When the data transfer causing the DTCCTj register value to change to 0 is
performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), an interrupt request
for the CPU is generated during DTC operation.
The lower 8 bits of the initial value for the repeat area address must be 00h. The size of data to be transferred
must be set to 255 bytes or less before the specified number of transfer times is completed.
Table 15.7 shows Register Functions in Repeat Mode.
Figure 15.9 shows Data Transfers in Repeat Mode.
Repeat Mode
DTCCTj register ≠ 1
DTCCTj register = 1
Register
Register Functions in Repeat Mode
Data Transfers in Repeat Mode
SRC0: Initial source address value
DST0: Initial destination address value
X: 0 or 1
X: 0 or 1
DTCCR register
DTCCR register
Bits b3 to b0 in
Bits b3 to b0 in
0X11b
1X11b
X001b
X101b
0X11b
1X11b
X001b
X101b
Transfer source
SRC
Source address
Source address
Repeat area
Repeat area
Incremented
Repeat area
Repeat area
Incremented
control
control
Fixed
Fixed
DTBLSj
DTCCTj
DTSARj
DTDARj
Symbol
Destination address
Destination address
Transfer
Incremented
Repeat area
Repeat area
Incremented
Repeat area
Repeat area
control
control
Fixed
Fixed
SRC0/DST0
Repeat area
SRC/DST
Size of the data block to be transferred by one activation
Number of times of data transfers
This register value is reloaded to the DTCCT register. (Data
transfer count is initialized.)
Data transfer source address
Data transfer destination address
Transfer destination
DST
Source address
Source address
after transfer
after transfer
SRC+N
SRC+N
SRC+N
SRC+N
SRC0
SRC0
SRC
SRC
Address of the repeat area is initialized
after a transfer.
DTBLSj = N
DTCCTj = 1
DTSARj = SRC
DTDARj = DST
j = 0 to 23
Size of the data block to be transferred by
one activation (N bytes)
DTBLSj = N
DTCCTj ≠ 1
DTSARj = SRC
DTDARj = DST
j = 0 to 23
Destination address
Destination address
Function
after transfer
after transfer
DST+N
DST+N
DST+N
DST+N
DST0
DST0
DST
DST
15. DTC