R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 247

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 214 of 723
15.4
15.4.1
15.4.2
15.4.3
15.4.4
• Do not generate any DTC activation sources before entering wait mode or during wait mode.
• Do not generate any DTC activation sources before entering stop mode or during stop mode.
• Modify bits DTCENi0 to DTCENi7 only while an interrupt request corresponding to the bit is not generated.
• When the interrupt source flag in the status register for the peripheral function is 1, do not modify the
• Do not access the DTCENi registers using DTC transfers.
• Do not set the status register bit for the peripheral function to 0 using a DTC transfer.
• When the DTC activation source is SSU/I
• When the DTC activation source is SSU/I
No interrupt is generated for the CPU during DTC operation in any of the following cases:
- When the DTC activation source is SSU/I
- When performing the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 in normal
- When performing the data transfer causing the DTCCRj register value to change to 0 while the RPTINT bit in
mode
the DTCCRj register is 1 (interrupt generation enabled) in repeat mode
corresponding activation source bit among bits DTCENi0 to DTCENi7.
register using a DTC transfer.
The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in SSRDR/ICDRR register) by
reading the SSRDR register/the ICDRR register.
However, the RDRF bit is not set to 0 by reading the SSRDR register/the ICDRR register when the DTC data
transfer setting is either of the following:
register using a DTC transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not
transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT
register.
- Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCRj register value to change from 1 to 0 while the RPTINT bit in the DTCCRj
Notes on DTC
register is 1 (interrupt generation enabled) in repeat mode
DTC activation source
DTCENi (i = 0 to 6) Registers
Peripheral Modules
Interrupt Request
2
2
C bus transmit data empty, write to the SSTDR register/the ICDRT
C transmit data empty or flash ready status
2
C bus receive data full, read the SSRDR register/the ICDRR
15. DTC