R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 323

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 290 of 723
19.6.2
Notes:
Table 19.12
h = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Note:
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
After Reset
1. Enabled when in PWM mode.
2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to
3. Enabled when in PWM2 mode.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Register
1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM
Address 0130h
19.9.6 TRCMR Register in PWM2 Mode.
Symbol TCEG1
period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.
Symbol
TCEG0 TRCTRG input edge select bit
TCEG1
Bit
POLB
POLC
POLD
CSEL
Timer RC Control Register 2 (TRCCR2) in PWM Mode
—
—
−
−
BFC = 0
BFD = 0
BFC = 1
BFD = 1
Functions of TRCGRh Register in PWM Mode
b7
0
Setting
PWM mode output level control
bit B
PWM mode output level control
bit C
PWM mode output level control
bit D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
TRC count operation select bit
(1)
(1)
(1)
TCEG0
b6
0
General register. Set the PWM period.
General register. Set the PWM output change point.
General register. Set the PWM output change point.
Buffer register. Set the next PWM period. (Refer to 19.3.2 Buffer
Operation.)
Buffer register. Set the next PWM output change point. (Refer to
19.3.2 Buffer Operation.)
Bit Name
CSEL
b5
0
b4
—
(3)
(2)
1
Register Function
0: TRCIOB output level selected as “L” active
1: TRCIOB output level selected as “H” active
0: TRCIOC output level selected as “L” active
1: TRCIOC output level selected as “H” active
0: TRCIOD output level selected as “L” active
1: TRCIOD output level selected as “H” active
0: Count continues at compare match with the
1: Count stops at compare match with the TRCGRA
b7 b6
0 0: Disable the trigger input from the TRCTRG pin
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
TRCGRA register
register
b3
—
1
POLD
b2
0
Function
POLC
b1
0
POLB
b0
0
−
TRCIOB
TRCIOC
TRCIOD
−
TRCIOB
PWM Output Pin
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—