R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 332

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 299 of 723
Figure 19.18
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output by compare match with the TRCGRC register, “L” output by compare match with the
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
TRCGRD register
TRCGRB register
TRCCR2 register
TRCGRB register).
TRCMR register
TRCSR register
TRCSR register
TRCSR register
TRCIOB output
TRCTRG input
Count source
TSTART bit in
CSEL bit in
IMFC bit in
IMFA bit in
IMFB bit in
FFFFh
TRC register value
0000h
m
n
p
“L” initial output
Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)
n
“H” output at
TRCGRC register
compare match
Transfer from buffer register to general register
n+1
p+1
Count starts
TSTART bit
is set to 1
Transfer
“L” output at
TRCGRB register
compare match
n
Set to 0 by
a program
n
Inactive level so
TRCTRG input is
enabled
Previous value
TSTART bit is
p+1
TRC register (counter)
cleared at TRCTRG pin
trigger input
Changed by a program
held if the
Transfer
set to 0
Return to initial value if the
TSTART bit is set to 0
n
Set to 0 by
a program
Set to 1 by
a program
Transfer from buffer register to general register
Set to 0000h
by a program
m+1
n+1
p+1
Transfer
Active level so TRCTRG
input is disabled
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
Count starts at
TRCTRG pin
trigger input
n
Set to 0 by
a program
Next data
TRC register cleared
at TRCGRA register
compare match
Set to 0 by
a program
19. Timer RC
Count stops
because the
CSEL bit is
set to 1
The TSTART
bit is set to 0
Transfer