R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 339

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 306 of 723
20.2
Figure 20.2
20.2.1
Table 20.3
i = 0 or 1
Note:
f1, f2, f4, f8, f32
fOCO40M
fOCO-F
fC2
External signal input
to TRDCLK pin
1. The count source fOCO40M can be used with VCC = 2.7 to 5.5 V.
TRDCLK/
TRDIOA0
Count Source
The count source selection method is the same in all modes. However, fC2 cannot be selected in PWM, reset
synchronous PWM, complementary PWM, or PWM3 mode. The external clock cannot be selected in PWM3
mode.
Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation
clock of timer RD (refer to Table 20.1 Timer RD Operation Clocks).
When selecting fOCO40M or fOCO-F for the count source, set the FRA00 bit in the FRA0 register to 1 (high-
speed on-chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 110b
(fOCO40M) or 111b (fOCO-F).
Common Items for Multiple Modes
Count Sources
(1)
Count Source Selection
Block Diagram of Count Source
STCLK = 1
STCLK = 0
fOCO40M
fOCO-F
fC2
f32
f1
f2
f4
f8
The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator
frequency).
Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).
Bits TCK2 to TCK0 in the TRDCRi register is set to 111b (fOCO-F).
Bits TCK2 to TCK0 in the TRDCRi register is set to 101b (TRDCLKi input or fC2)
The ITCLKi bit in the TRDECR register is set to 1 (fC2)
The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b
(count source: external clock).
The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.
The PD2_0 bit in the PD2 register is set to 0 (input mode).
ITCLK0, ITCLK1: Bits in TRDECR register
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register
STCLK: Bit in TRDFCR register
ITCLKi = 0
ITCLKi = 1
TRDIOA0 I/O or programmable I/O port
CKEG1 to CKEG0
Valid edge
selected
= 011b
= 100b
= 110b
= 010b
= 111b
= 001b
TCK2 to TCK0
= 000b
= 101b
Selection
Count source
TRDi register
20. Timer RD