R5F21346CNFP#U0 Renesas Electronics America, R5F21346CNFP#U0 Datasheet - Page 343

• Manufacturer Part Number: R5F21346CNFP#U0
• Description: MCU 1KB FLASH 32K ROM 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/34Cr

Specifications of R5F21346CNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 43
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/34C Group
REJ09B0586-0100 Rev.1.00 Jan 13, 2010
Page 310 of 723
20.2.4
In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and
PWM3 mode, the TRDIOji (i = 0 or 1, j = A, B, C, or D) output pin can be forcibly set to a programmable I/O
port by the INT0 pin input, and pulse output can be cut off.
The pins used for output in these functions or modes can function as the output pin of timer RD when the
applicable bit in the TRDOER1 register is set to 0 (enable timer RD output). When the PTO bit in the
TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled), all bits in the TRDOER1
register are set to 1 (disable timer RD output, the TRDIOji output pin is used as the programmable I/O port)
after “L” is applied to the INT0 pin. The TRDIOji output pin is set to the programmable I/O port after “L” is
applied to the INT0 pin and waiting for 1 to 2 cycles of the timer RD operation clock (refer to Table 20.1
Timer RD Operation Clocks).
Make the following settings to use this function:
• Set the pin status (high impedance, “L” or “H” output) to pulse output forced cutoff by registers P2 and PD2.
• Set the INT0EN bit in the INTEN register to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge), and
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF register.
• Set the PTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled).
The IR bit in the INT0IC register is set to 1 (interrupt requested) in accordance with the setting of the POL bit in
the INT0IC register and the INT0PL bit in the INTEN register and a change in the INT0 pin input (refer to 11.8
Notes on Interrupts).
For details on interrupts, refer to 11. Interrupts.
set the POL bit in the INT0IC register to 0 (falling edge selected).
Pulse Output Forced Cutoff
20. Timer RD